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ATMEGA48PA-AU 参数 Datasheet PDF下载

ATMEGA48PA-AU图片预览
型号: ATMEGA48PA-AU
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器与4/8/ 16 / 32K字节的系统内可编程闪存 [8-bit Microcontroller with 4/8/16/32K Bytes In-System Programmable Flash]
分类和应用: 闪存微控制器和处理器外围集成电路时钟
文件页数/大小: 448 页 / 12817 K
品牌: ATMEL [ ATMEL ]
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ATmega48PA/88PA/168PA/328P  
Table 13-2 summarizes the function of the overriding signals. The pin and port indexes from Fig-  
ure 13-5 on page 80 are not shown in the succeeding tables. The overriding signals are  
generated internally in the modules having the alternate function.  
Table 13-2. Generic Description of Overriding Signals for Alternate Functions  
Signal Name  
Full Name  
Description  
If this signal is set, the pull-up enable is controlled by the PUOV  
signal. If this signal is cleared, the pull-up is enabled when  
{DDxn, PORTxn, PUD} = 0b010.  
Pull-up Override  
Enable  
PUOE  
If PUOE is set, the pull-up is enabled/disabled when PUOV is  
set/cleared, regardless of the setting of the DDxn, PORTxn,  
and PUD Register bits.  
Pull-up Override  
Value  
PUOV  
DDOE  
DDOV  
If this signal is set, the Output Driver Enable is controlled by the  
DDOV signal. If this signal is cleared, the Output driver is  
enabled by the DDxn Register bit.  
Data Direction  
Override Enable  
If DDOE is set, the Output Driver is enabled/disabled when  
DDOV is set/cleared, regardless of the setting of the DDxn  
Register bit.  
Data Direction  
Override Value  
If this signal is set and the Output Driver is enabled, the port  
value is controlled by the PVOV signal. If PVOE is cleared, and  
the Output Driver is enabled, the port Value is controlled by the  
PORTxn Register bit.  
Port Value  
Override Enable  
PVOE  
Port Value  
Override Value  
If PVOE is set, the port value is set to PVOV, regardless of the  
setting of the PORTxn Register bit.  
PVOV  
PTOE  
Port Toggle  
Override Enable  
If PTOE is set, the PORTxn Register bit is inverted.  
Digital Input  
Enable Override  
Enable  
If this bit is set, the Digital Input Enable is controlled by the  
DIEOV signal. If this signal is cleared, the Digital Input Enable  
is determined by MCU state (Normal mode, sleep mode).  
DIEOE  
DIEOV  
Digital Input  
Enable Override  
Value  
If DIEOE is set, the Digital Input is enabled/disabled when  
DIEOV is set/cleared, regardless of the MCU state (Normal  
mode, sleep mode).  
This is the Digital Input to alternate functions. In the figure, the  
signal is connected to the output of the Schmitt Trigger but  
before the synchronizer. Unless the Digital Input is used as a  
clock source, the module with the alternate function will use its  
own synchronizer.  
DI  
Digital Input  
This is the Analog Input/output to/from alternate functions. The  
signal is connected directly to the pad, and can be used bi-  
directionally.  
Analog  
Input/Output  
AIO  
The following subsections shortly describe the alternate functions for each port, and relate the  
overriding signals to the alternate function. Refer to the alternate function description for further  
details.  
81  
8161D–AVR–10/09