ATmega48PA/88PA/168PA/328P
9.11 Register Description
9.11.1
SMCR – Sleep Mode Control Register
The Sleep Mode Control Register contains control bits for power management.
Bit
7
–
6
–
5
–
4
–
3
2
1
0
SE
R/W
0
0x33 (0x53)
Read/Write
Initial Value
SM2
R/W
0
SM1
R/W
0
SM0
R/W
0
SMCR
R
0
R
0
R
0
R
0
• Bits 7..4 Res: Reserved Bits
These bits are unused in the ATmega48PA/88PA/168PA/328P, and will always be read as zero.
• Bits 3..1 – SM2..0: Sleep Mode Select Bits 2, 1, and 0
These bits select between the five available sleep modes as shown in Table 9-2.
Table 9-2.
Sleep Mode Select
SM2
0
SM1
SM0
Sleep Mode
Idle
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
ADC Noise Reduction
Power-down
Power-save
Reserved
0
0
1
1
Reserved
1
Standby(1)
1
External Standby(1)
Note:
1. Standby mode is only recommended for use with external crystals or resonators.
• Bit 0 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s
purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of
the SLEEP instruction and to clear it immediately after waking up.
9.11.2
MCUCR – MCU Control Register
Bit
0x35 (0x55)
7
6
BODS
R
5
4
3
–
2
–
1
IVSEL
R/W
0
0
IVCE
R/W
0
–
BODSE
PUD
R/W
0
MCUCR
Read/Write
Initial Value
R
0
R
0
R
0
R
0
0
• Bit 6 – BODS: BOD Sleep
The BODS bit must be written to logic one in order to turn off BOD during sleep, see Table 9-1
on page 39. Writing to the BODS bit is controlled by a timed sequence and an enable bit,
BODSE in MCUCR. To disable BOD in relevant sleep modes, both BODS and BODSE must first
44
8161D–AVR–10/09
ATMEL [ ATMEL ]
