ATmega128A
6. Instruction Set Summary (Continued)
SES
Set Signed Test Flag
S ← 1
S ← 0
S
S
1
1
CLS
Clear Signed Test Flag
Mnemonics
Operands
Description
Operation
Flags
#Clocks
SEV
CLV
SET
CLT
SEH
CLH
Set Twos Complement Overflow.
Clear Twos Complement Overflow
Set T in SREG
V ← 1
V ← 0
T ← 1
T ← 0
H ← 1
H ← 0
V
V
T
T
H
H
1
1
1
1
1
1
Clear T in SREG
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
MCU CONTROL INSTRUCTIONS
NOP
No Operation
Sleep
None
None
None
None
1
1
SLEEP
WDR
(see specific descr. for Sleep function)
(see specific descr. for WDR/timer)
For On-chip Debug Only
Watchdog Reset
Break
1
BREAK
N/A
19
8151GS–AVR–07/10