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ATMEGA48V-10AUR 参数 Datasheet PDF下载

ATMEGA48V-10AUR图片预览
型号: ATMEGA48V-10AUR
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 10MHz, CMOS, PQFP32, 7 X 7 MM, 1 MM HEIGHT, 0.80 MM PITCH, GREEN, PLASTIC, MS-026ABA, TQFP-32]
分类和应用: 闪存微控制器
文件页数/大小: 376 页 / 4764 K
品牌: ATMEL [ ATMEL ]
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27.8.1  
Serial Programming Pin Mapping  
Table 27-15. Pin Mapping Serial Programming  
Symbol  
MOSI  
MISO  
SCK  
Pins  
PB3  
PB4  
PB5  
I/O  
Description  
Serial Data in  
Serial Data out  
Serial Clock  
I
O
I
27.8.2  
Serial Programming Algorithm  
When writing serial data to the ATmega48/88/168, data is clocked on the rising edge of SCK.  
When reading data from the ATmega48/88/168, data is clocked on the falling edge of SCK. See  
Figure 27-9 for timing details.  
To program and verify the ATmega48/88/168 in the serial programming mode, the following  
sequence is recommended (See Serial Programming Instruction set in Table 27-17 on page  
301):  
1. Power-up sequence:  
Apply power between VCC and GND while RESET and SCK are set to “0”. In some sys-  
tems, the programmer can not guarantee that SCK is held low during power-up. In this  
case, RESET must be given a positive pulse of at least two CPU clock cycles duration  
after SCK has been set to “0”.  
2. Wait for at least 20 ms and enable serial programming by sending the Programming  
Enable serial instruction to pin MOSI.  
3. The serial programming instructions will not work if the communication is out of synchro-  
nization. When in sync. the second byte (0x53), will echo back when issuing the third  
byte of the Programming Enable instruction. Whether the echo is correct or not, all four  
bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a  
positive pulse and issue a new Programming Enable command.  
4. The Flash is programmed one page at a time. The memory page is loaded one byte at a  
time by supplying the 6 LSB of the address and data together with the Load Program  
Memory Page instruction. To ensure correct loading of the page, the data low byte must  
be loaded before data high byte is applied for a given address. The Program Memory  
Page is stored by loading the Write Program Memory Page instruction with the 7 MSB of  
the address. If polling (RDY/BSY) is not used, the user must wait at least tWD_FLASH before  
issuing the next page (See Table 27-16). Accessing the serial programming interface  
before the Flash write operation completes can result in incorrect programming.  
5. A: The EEPROM array is programmed one byte at a time by supplying the address and  
data together with the appropriate Write instruction. An EEPROM memory location is first  
automatically erased before new data is written. If polling (RDY/BSY) is not used, the  
user must wait at least tWD_EEPROM before issuing the next byte (See Table 27-16). In a  
chip erased device, no 0xFFs in the data file(s) need to be programmed.  
B: The EEPROM array is programmed one page at a time. The Memory page is loaded  
one byte at a time by supplying the 6 LSB of the address and data together with the Load  
EEPROM Memory Page instruction. The EEPROM Memory Page is stored by loading  
the Write EEPROM Memory Page Instruction with the 7 MSB of the address. When using  
EEPROM page access only byte locations loaded with the Load EEPROM Memory Page  
instruction is altered. The remaining locations remain unchanged. If polling (RDY/BSY) is  
not used, the used must wait at least tWD_EEPROM before issuing the next byte (See Table  
27-16). In a chip erased device, no 0xFF in the data file(s) need to be programmed.  
300  
ATmega48/88/168  
2545M–AVR–09/07  
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