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ATMEGA48V-10AUR 参数 Datasheet PDF下载

ATMEGA48V-10AUR图片预览
型号: ATMEGA48V-10AUR
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 10MHz, CMOS, PQFP32, 7 X 7 MM, 1 MM HEIGHT, 0.80 MM PITCH, GREEN, PLASTIC, MS-026ABA, TQFP-32]
分类和应用: 闪存微控制器
文件页数/大小: 376 页 / 4764 K
品牌: ATMEL [ ATMEL ]
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ATmega48/88/168  
26.4 Read-While-Write and No Read-While-Write Flash Sections  
Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot Loader soft-  
ware update is dependent on which address that is being programmed. In addition to the two  
sections that are configurable by the BOOTSZ Fuses as described above, the Flash is also  
divided into two fixed sections, the Read-While-Write (RWW) section and the No Read-While-  
Write (NRWW) section. The limit between the RWW- and NRWW sections is given in Table 26-  
7 on page 282 and Figure 26-2 on page 273. The main difference between the two sections is:  
• When erasing or writing a page located inside the RWW section, the NRWW section can be  
read during the operation.  
• When erasing or writing a page located inside the NRWW section, the CPU is halted during the  
entire operation.  
Note that the user software can never read any code that is located inside the RWW section dur-  
ing a Boot Loader software operation. The syntax “Read-While-Write section” refers to which  
section that is being programmed (erased or written), not which section that actually is being  
read during a Boot Loader software update.  
26.4.1  
RWW – Read-While-Write Section  
If a Boot Loader software update is programming a page inside the RWW section, it is possible  
to read code from the Flash, but only code that is located in the NRWW section. During an on-  
going programming, the software must ensure that the RWW section never is being read. If the  
user software is trying to read code that is located inside the RWW section (i.e., by a  
call/jmp/lpm or an interrupt) during programming, the software might end up in an unknown  
state. To avoid this, the interrupts should either be disabled or moved to the Boot Loader sec-  
tion. The Boot Loader section is always located in the NRWW section. The RWW Section Busy  
bit (RWWSB) in the Store Program Memory Control and Status Register (SPMCSR) will be read  
as logical one as long as the RWW section is blocked for reading. After a programming is com-  
pleted, the RWWSB must be cleared by software before reading code located in the RWW  
section. See “SPMCSR – Store Program Memory Control and Status Register” on page 284. for  
details on how to clear RWWSB.  
26.4.2  
NRWW – No Read-While-Write Section  
The code located in the NRWW section can be read when the Boot Loader software is updating  
a page in the RWW section. When the Boot Loader code updates the NRWW section, the CPU  
is halted during the entire Page Erase or Page Write operation.  
Table 26-1. Read-While-Write Features  
Which Section does the Z-  
pointer Address during  
the Programming?  
Which Section can be  
read during  
Read-While-Write  
Supported?  
Programming?  
CPU Halted?  
RWW Section  
NRWW Section  
None  
No  
Yes  
No  
NRWW Section  
Yes  
271  
2545M–AVR–09/07  
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