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ATMEGA48V-10AUR 参数 Datasheet PDF下载

ATMEGA48V-10AUR图片预览
型号: ATMEGA48V-10AUR
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 10MHz, CMOS, PQFP32, 7 X 7 MM, 1 MM HEIGHT, 0.80 MM PITCH, GREEN, PLASTIC, MS-026ABA, TQFP-32]
分类和应用: 闪存微控制器
文件页数/大小: 376 页 / 4764 K
品牌: ATMEL [ ATMEL ]
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ATmega48/88/168  
The TWINT Flag is set in the following situations:  
• After the TWI has transmitted a START/REPEATED START condition.  
• After the TWI has transmitted SLA+R/W.  
• After the TWI has transmitted an address byte.  
• After the TWI has lost arbitration.  
• After the TWI has been addressed by own slave address or general call.  
• After the TWI has received a data byte.  
• After a STOP or REPEATED START has been received while still addressed as a Slave.  
• When a bus error has occurred due to an illegal START or STOP condition.  
21.6 Using the TWI  
The AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like  
reception of a byte or transmission of a START condition. Because the TWI is interrupt-based,  
the application software is free to carry on other operations during a TWI byte transfer. Note that  
the TWI Interrupt Enable (TWIE) bit in TWCR together with the Global Interrupt Enable bit in  
SREG allow the application to decide whether or not assertion of the TWINT Flag should gener-  
ate an interrupt request. If the TWIE bit is cleared, the application must poll the TWINT Flag in  
order to detect actions on the TWI bus.  
When the TWINT Flag is asserted, the TWI has finished an operation and awaits application  
response. In this case, the TWI Status Register (TWSR) contains a value indicating the current  
state of the TWI bus. The application software can then decide how the TWI should behave in  
the next TWI bus cycle by manipulating the TWCR and TWDR Registers.  
Figure 21-10 is a simple example of how the application can interface to the TWI hardware. In  
this example, a Master wishes to transmit a single data byte to a Slave. This description is quite  
abstract, a more detailed explanation follows later in this section. A simple code example imple-  
menting the desired behavior is also presented.  
Figure 21-10. Interfacing the Application to the TWI in a Typical Transmission  
3. Check TWSR to see if START was  
sent. Application loads SLA+W into  
TWDR, and loads appropriate control  
signals into TWCR, makin sure that  
TWINT is written to one,  
5. Check TWSR to see if SLA+W was  
sent and ACK received.  
Application loads data into TWDR, and  
loads appropriate control signals into  
TWCR, making sure that TWINT is  
written to one  
1. Application  
writes to TWCR to  
initiate  
transmission of  
START  
7. Check TWSR to see if data was sent  
and ACK received.  
Application loads appropriate control  
signals to send STOP into TWCR,  
making sure that TWINT is written to one  
and TWSTA is written to zero.  
TWI bus START  
SLA+W  
A
Data  
A
STOP  
Indicates  
TWINT set  
4. TWINT set.  
Status code indicates  
SLA+W sent, ACK  
received  
2. TWINT set.  
Status code indicates  
START condition sent  
6. TWINT set.  
Status code indicates  
data sent, ACK received  
1. The first step in a TWI transmission is to transmit a START condition. This is done by  
writing a specific value into TWCR, instructing the TWI hardware to transmit a START  
219  
2545M–AVR–09/07  
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