ATmega48/88/168
Note:
1. The baud rate is defined to be the transfer rate in bit per second (bps)
BAUD
fOSC
Baud rate (in bits per second, bps)
System Oscillator clock frequency
UBRRn
Contents of the UBRRnH and UBRRnL Registers, (0-4095)
20.4 SPI Data Modes and Timing
There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which
are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are
shown in Figure 20-1. Data bits are shifted out and latched in on opposite edges of the XCKn
signal, ensuring sufficient time for data signals to stabilize. The UCPOLn and UCPHAn function-
ality is summarized in Table 20-2. Note that changing the setting of any of these bits will corrupt
all ongoing communication for both the Receiver and Transmitter.
Table 20-2. UCPOLn and UCPHAn Functionality-
UCPOLn
UCPHAn
SPI Mode
Leading Edge
Sample (Rising)
Setup (Rising)
Sample (Falling)
Setup (Falling)
Trailing Edge
Setup (Falling)
Sample (Falling)
Setup (Rising)
Sample (Rising)
0
0
1
1
0
1
0
1
0
1
2
3
Figure 20-1. UCPHAn and UCPOLn data transfer timing diagrams.
UCPOL=0
UCPOL=1
XCK
XCK
Data setup (TXD)
Data sample (RXD)
Data setup (TXD)
Data sample (RXD)
XCK
XCK
Data setup (TXD)
Data sample (RXD)
Data setup (TXD)
Data sample (RXD)
20.5 Frame Formats
A serial frame for the MSPIM is defined to be one character of 8 data bits. The USART in MSPIM
mode has two valid frame formats:
• 8-bit data with MSB first
• 8-bit data with LSB first
A frame starts with the least or most significant data bit. Then the next data bits, up to a total of
eight, are succeeding, ending with the most or least significant bit accordingly. When a complete
frame is transmitted, a new frame can directly follow it, or the communication line can be set to
an idle (high) state.
201
2545M–AVR–09/07
ATMEL [ ATMEL ]
