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ATMEGA48V-10AUR 参数 Datasheet PDF下载

ATMEGA48V-10AUR图片预览
型号: ATMEGA48V-10AUR
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 10MHz, CMOS, PQFP32, 7 X 7 MM, 1 MM HEIGHT, 0.80 MM PITCH, GREEN, PLASTIC, MS-026ABA, TQFP-32]
分类和应用: 闪存微控制器
文件页数/大小: 376 页 / 4764 K
品牌: ATMEL [ ATMEL ]
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20. USART in SPI Mode  
20.1 Features  
Full Duplex, Three-wire Synchronous Data Transfer  
Master Operation  
Supports all four SPI Modes of Operation (Mode 0, 1, 2, and 3)  
LSB First or MSB First Data Transfer (Configurable Data Order)  
Queued Operation (Double Buffered)  
High Resolution Baud Rate Generator  
High Speed Operation (fXCKmax = fCK/2)  
Flexible Interrupt Generation  
20.2 Overview  
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) can be  
set to a master SPI compliant mode of operation. Setting both UMSELn1:0 bits to one enables  
the USART in Master SPI Mode (MSPIM) logic. In this mode of operation the SPI master control  
logic takes direct control over the USART resources. These resources include the transmitter  
and receiver shift register and buffers, and the baud rate generator. The parity generator and  
checker, the data and clock recovery logic, and the RX and TX control logic is disabled. The  
USART RX and TX control logic is replaced by a common SPI transfer control logic. However,  
the pin control logic and interrupt generation logic is identical in both modes of operation.  
The I/O register locations are the same in both modes. However, some of the functionality of the  
control registers changes when using MSPIM.  
20.3 Clock Generation  
The Clock Generation logic generates the base clock for the Transmitter and Receiver. For  
USART MSPIM mode of operation only internal clock generation (i.e. master operation) is sup-  
ported. The Data Direction Register for the XCKn pin (DDR_XCKn) must therefore be set to one  
(i.e. as output) for the USART in MSPIM to operate correctly. Preferably the DDR_XCKn should  
be set up before the USART in MSPIM is enabled (i.e. TXENn and RXENn bit set to one).  
The internal clock generation used in MSPIM mode is identical to the USART synchronous mas-  
ter mode. The baud rate or UBRRn setting can therefore be calculated using the same  
equations, see Table 20-1:  
Table 20-1. Equations for Calculating Baud Rate Register Setting  
Equation for Calculating Baud  
Rate(1)  
Equation for Calculating UBRRn  
Value  
Operating Mode  
Synchronous Master  
mode  
f
OSC  
f
OSC  
BAUD = --------------------------------------  
UBRRn = -------------------- 1  
2(UBRRn + 1)  
2BAUD  
200  
ATmega48/88/168  
2545M–AVR–09/07  
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