欢迎访问ic37.com |
会员登录 免费注册
发布采购

ATMEGA48V-10AUR 参数 Datasheet PDF下载

ATMEGA48V-10AUR图片预览
型号: ATMEGA48V-10AUR
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 10MHz, CMOS, PQFP32, 7 X 7 MM, 1 MM HEIGHT, 0.80 MM PITCH, GREEN, PLASTIC, MS-026ABA, TQFP-32]
分类和应用: 闪存微控制器
文件页数/大小: 376 页 / 4764 K
品牌: ATMEL [ ATMEL ]
 浏览型号ATMEGA48V-10AUR的Datasheet PDF文件第173页浏览型号ATMEGA48V-10AUR的Datasheet PDF文件第174页浏览型号ATMEGA48V-10AUR的Datasheet PDF文件第175页浏览型号ATMEGA48V-10AUR的Datasheet PDF文件第176页浏览型号ATMEGA48V-10AUR的Datasheet PDF文件第178页浏览型号ATMEGA48V-10AUR的Datasheet PDF文件第179页浏览型号ATMEGA48V-10AUR的Datasheet PDF文件第180页浏览型号ATMEGA48V-10AUR的Datasheet PDF文件第181页  
ATmega48/88/168  
A frame starts with the start bit followed by the least significant data bit. Then the next data bits,  
up to a total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit  
is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it can  
be directly followed by a new frame, or the communication line can be set to an idle (high) state.  
Figure 19-4 illustrates the possible combinations of the frame formats. Bits inside brackets are  
optional.  
Figure 19-4. Frame Formats  
FRAME  
(IDLE)  
St  
0
1
2
3
4
[5]  
[6]  
[7]  
[8]  
[P] Sp1 [Sp2] (St / IDLE)  
St  
Start bit, always low.  
Data bits (0 to 8).  
(n)  
P
Parity bit. Can be odd or even.  
Stop bit, always high.  
Sp  
IDLE  
must be  
No transfers on the communication line (RxDn or TxDn). An IDLE line  
high.  
The frame format used by the USART is set by the UCSZn2:0, UPMn1:0 and USBSn bits in  
UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting. Note that changing  
the setting of any of these bits will corrupt all ongoing communication for both the Receiver and  
Transmitter.  
The USART Character SiZe (UCSZn2:0) bits select the number of data bits in the frame. The  
USART Parity mode (UPMn1:0) bits enable and set the type of parity bit. The selection between  
one or two stop bits is done by the USART Stop Bit Select (USBSn) bit. The Receiver ignores  
the second stop bit. An FE (Frame Error) will therefore only be detected in the cases where the  
first stop bit is zero.  
19.4.1  
Parity Bit Calculation  
The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the  
result of the exclusive or is inverted. The relation between the parity bit and data bits is as  
follows:  
P
P
= d  
= d  
⊕ … ⊕ d d d d 0  
3 2 1 0  
even  
n 1  
n 1  
⊕ … ⊕ d d d d 1  
odd  
3 2 1 0  
Peven  
Podd  
dn  
Parity bit using even parity  
Parity bit using odd parity  
Data bit n of the character  
If used, the parity bit is located between the last data bit and first stop bit of a serial frame.  
177  
2545M–AVR–09/07  
 复制成功!