ATmega48/88/168
Figure 19-1. USART Block Diagram(1)
Clock Generator
UBRRn[H:L]
OSC
BAUD RATE GENERATOR
SYNC LOGIC
PIN
CONTROL
XCKn
Transmitter
TX
CONTROL
UDRn(Transmit)
PARITY
GENERATOR
PIN
TxDn
TRANSMIT SHIFT REGISTER
CONTROL
Receiver
CLOCK
RECOVERY
RX
CONTROL
DATA
RECOVERY
PIN
CONTROL
RECEIVE SHIFT REGISTER
RxDn
PARITY
CHECKER
UDRn(Receive)
UCSRnA
UCSRnB
UCSRnC
Note:
1. Refer to Figure 1-1 on page 2 and Table 13-9 on page 85 for USART0 pin placement.
19.3 Clock Generation
The Clock Generation logic generates the base clock for the Transmitter and Receiver. The
USART supports four modes of clock operation: Normal asynchronous, Double Speed asyn-
chronous, Master synchronous and Slave synchronous mode. The UMSELn bit in USART
Control and Status Register C (UCSRnC) selects between asynchronous and synchronous
operation. Double Speed (asynchronous mode only) is controlled by the U2Xn found in the
UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register
for the XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or
external (Slave mode). The XCKn pin is only active when using synchronous mode.
Figure 19-2 shows a block diagram of the clock generation logic.
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2545M–AVR–09/07
ATMEL [ ATMEL ]
