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ATMEGA8A-AUR 参数 Datasheet PDF下载

ATMEGA8A-AUR图片预览
型号: ATMEGA8A-AUR
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 16MHz, CMOS, PQFP32, 7 X 7 MM, 1 MM HEIGHT, 0.80 MM PITCH, GREEN, PLASTIC, MS-026ABA, TQFP-32]
分类和应用: 闪存
文件页数/大小: 308 页 / 4674 K
品牌: ATMEL [ ATMEL ]
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By writing the TWEA bit to zero, the device can be virtually disconnected from the Two-wire  
Serial Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one  
again.  
• Bit 5 – TWSTA: TWI START Condition Bit  
The application writes the TWSTA bit to one when it desires to become a Master on the Two-  
wire Serial Bus. The TWI hardware checks if the bus is available, and generates a START con-  
dition on the bus if it is free. However, if the bus is not free, the TWI waits until a STOP condition  
is detected, and then generates a new START condition to claim the bus Master status. TWSTA  
must be cleared by software when the START condition has been transmitted.  
• Bit 4 – TWSTO: TWI STOP Condition Bit  
Writing the TWSTO bit to one in Master mode will generate a STOP condition on the Two-wire  
Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared auto-  
matically. In Slave mode, setting the TWSTO bit can be used to recover from an error condition.  
This will not generate a STOP condition, but the TWI returns to a well-defined unaddressed  
Slave mode and releases the SCL and SDA lines to a high impedance state.  
• Bit 3 – TWWC: TWI Write Collision Flag  
The TWWC bit is set when attempting to write to the TWI Data Register – TWDR when TWINT is  
low. This flag is cleared by writing the TWDR Register when TWINT is high.  
• Bit 2 – TWEN: TWI Enable Bit  
The TWEN bit enables TWI operation and activates the TWI interface. When TWEN is written to  
one, the TWI takes control over the I/O pins connected to the SCL and SDA pins, enabling the  
slew-rate limiters and spike filters. If this bit is written to zero, the TWI is switched off and all TWI  
transmissions are terminated, regardless of any ongoing operation.  
• Bit 1 – Res: Reserved Bit  
This bit is a reserved bit and will always read as zero.  
• Bit 0 – TWIE: TWI Interrupt Enable  
When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be acti-  
vated for as long as the TWINT Flag is high.  
172  
ATmega8(L)  
2486T–AVR–05/08  
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