12.2 Register Description
12.2.1
EICRA – External Interrupt Control Register A
The External Interrupt Control Register A contains control bits for interrupt sense control.
Bit
7
–
6
–
5
–
4
–
3
ISC11
R/W
0
2
ISC10
R/W
0
1
ISC01
R/W
0
0
ISC00
R/W
0
(0x69)
EICRA
Read/Write
Initial Value
R
0
R
0
R
0
R
0
• Bit 7..4 – Res: Reserved Bits
These bits are unused bits in the ATmega48/88/168, and will always read as zero.
• Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT1 pin that activate the
interrupt are defined in Table 12-1. The value on the INT1 pin is sampled before detecting
edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will
generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level
interrupt is selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt.
Table 12-1. Interrupt 1 Sense Control
ISC11
ISC10
Description
0
0
1
1
0
1
0
1
The low level of INT1 generates an interrupt request.
Any logical change on INT1 generates an interrupt request.
The falling edge of INT1 generates an interrupt request.
The rising edge of INT1 generates an interrupt request.
• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined in Table 12-2. The value on the INT0 pin is sampled before detecting
edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will
generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level
interrupt is selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt.
Table 12-2. Interrupt 0 Sense Control
ISC01
ISC00
Description
0
0
1
1
0
1
0
1
The low level of INT0 generates an interrupt request.
Any logical change on INT0 generates an interrupt request.
The falling edge of INT0 generates an interrupt request.
The rising edge of INT0 generates an interrupt request.
68
ATmega48/88/168
2545M–AVR–09/07
ATMEL [ ATMEL ]
