ATmega48/88/168
Figure 10-1. Reset Logic
DATA BUS
MCU Status
Register (MCUSR)
Power-on Reset
Circuit
Brown-out
Reset Circuit
BODLEVEL [2..0]
Pull-up Resistor
SPIKE
FILTER
RSTDISBL
Watchdog
Oscillator
Delay Counters
Clock
CK
Generator
TIMEOUT
CKSEL[3:0]
SUT[1:0]
10.3 Power-on Reset
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level
is defined in “System and Reset Characteristics” on page 308. The POR is activated whenever
V
CC is below the detection level. The POR circuit can be used to trigger the start-up Reset, as
well as to detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the
Power-on Reset threshold voltage invokes the delay counter, which determines how long the
device is kept in RESET after VCC rise. The RESET signal is activated again, without any delay,
when VCC decreases below the detection level.
Figure 10-2. MCU Start-up, RESET Tied to VCC
VPOT
VCC
VRST
RESET
tTOUT
TIME-OUT
INTERNAL
RESET
47
2545M–AVR–09/07
ATMEL [ ATMEL ]
