16.1 Register Description
16.1.1
GTCCR – General Timer/Counter Control Register
Bit
7
6
–
5
–
4
–
3
–
2
–
1
PSRASY
R/W
0
PSRSYNC
R/W
0x23 (0x43)
Read/Write
Initial Value
TSM
R/W
0
GTCCR
R
0
R
0
R
0
R
0
R
0
0
0
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to the PSRASY and PSRSYNC bits is kept, hence keeping the correspond-
ing prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are
halted and can be configured to the same value without the risk of one of them advancing during
configuration. When the TSM bit is written to zero, the PSRASY and PSRSYNC bits are cleared
by hardware, and the Timer/Counters start counting simultaneously.
• Bit 0 – PSRSYNC: Prescaler Reset
When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is nor-
mally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1
and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both
timers.
140
ATmega48/88/168
2545M–AVR–09/07
ATMEL [ ATMEL ]
