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ATMEGA48V-10MMHR 参数 Datasheet PDF下载

ATMEGA48V-10MMHR图片预览
型号: ATMEGA48V-10MMHR
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 10MHz, CMOS, PQCC28, 4 X 4 MM, 1 MM HEIGHT, 0.45 MM PITCH, GREEN, PLASTIC, VQFN-28]
分类和应用: 闪存微控制器
文件页数/大小: 376 页 / 4764 K
品牌: ATMEL [ ATMEL ]
 浏览型号ATMEGA48V-10MMHR的Datasheet PDF文件第110页浏览型号ATMEGA48V-10MMHR的Datasheet PDF文件第111页浏览型号ATMEGA48V-10MMHR的Datasheet PDF文件第112页浏览型号ATMEGA48V-10MMHR的Datasheet PDF文件第113页浏览型号ATMEGA48V-10MMHR的Datasheet PDF文件第115页浏览型号ATMEGA48V-10MMHR的Datasheet PDF文件第116页浏览型号ATMEGA48V-10MMHR的Datasheet PDF文件第117页浏览型号ATMEGA48V-10MMHR的Datasheet PDF文件第118页  
Assembly Code Example(1)  
TIM16_WriteTCNT1:  
; Save global interrupt flag  
in r18,SREG  
; Disable interrupts  
cli  
; Set TCNT1 to r17:r16  
outTCNT1H,r17  
outTCNT1L,r16  
; Restore global interrupt flag  
outSREG,r18  
ret  
C Code Example(1)  
void TIM16_WriteTCNT1( unsigned int i )  
{
unsigned char sreg;  
unsigned int i;  
/* Save global interrupt flag */  
sreg = SREG;  
/* Disable interrupts */  
_CLI();  
/* Set TCNT1 to i */  
TCNT1 = i;  
/* Restore global interrupt flag */  
SREG = sreg;  
}
Note:  
1. See ”About Code Examples” on page 9.  
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”  
instructions must be replaced with instructions that allow access to extended I/O. Typically  
“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.  
The assembly code example requires that the r17:r16 register pair contains the value to be writ-  
ten to TCNT1.  
15.3.1  
Reusing the Temporary High Byte Register  
If writing to more than one 16-bit register where the high byte is the same for all registers written,  
then the high byte only needs to be written once. However, note that the same rule of atomic  
operation described previously also applies in this case.  
15.4 Timer/Counter Clock Sources  
The Timer/Counter can be clocked by an internal or an external clock source. The clock source  
is selected by the Clock Select logic which is controlled by the Clock Select (CS12:0) bits  
located in the Timer/Counter control Register B (TCCR1B). For details on clock sources and  
prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on page 138.  
114  
ATmega48/88/168  
2545M–AVR–09/07  
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