ATmega8(L)
• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits
These bits determine the division factor between the XTAL frequency and the input
clock to the ADC.
Table 76. ADC Prescaler Selections
ADPS2
ADPS1
ADPS0
Division Factor
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
2
4
8
16
32
64
128
The ADC Data Register – ADCL and ADCH
ADLAR = 0
Bit
15
14
13
12
11
10
9
8
–
–
–
–
–
–
ADC9
ADC8
ADCH
ADCL
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
7
R
R
0
6
R
R
0
5
R
R
0
4
R
R
0
3
R
R
0
2
R
R
0
1
R
R
0
0
R
R
0
Read/Write
Initial Value
0
0
0
0
0
0
0
0
ADLAR = 1
Bit
15
14
13
12
11
10
9
8
ADC9
ADC8
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADCH
ADCL
ADC1
ADC0
–
5
–
4
–
3
–
2
–
1
–
0
7
R
R
0
6
R
R
0
Read/Write
Initial Value
R
R
0
R
R
0
R
R
0
R
R
0
R
R
0
R
R
0
0
0
0
0
0
0
0
0
When an ADC conversion is complete, the result is found in these two registers.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Conse-
quently, if the result is left adjusted and no more than 8-bit precision is required, it is
sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is
read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared
(default), the result is right adjusted.
• ADC9:0: ADC Conversion result
These bits represent the result from the conversion, as detailed in “ADC Conversion
Result” on page 202.
205
2486M–AVR–12/03
ATMEL [ ATMEL ]
