ATmega8(L)
Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
Rd, Rr
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd
Add two Registers
Rd Rd + Rr
Z, C, N, V, H
Z, C, N, V, H
Z, C, N, V, S
Z, C, N, V, H
Z, C, N, V, H
Z, C, N, V, H
Z, C, N ,V, H
Z, C, N, V, S
Z, N, V
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
ADC
ADIW
SUB
Add with Carry two Registers
Add Immediate to Word
Subtract two Registers
Subtract Constant from Register
Subtract with Carry two Registers
Subtract with Carry Constant from Reg.
Subtract Immediate from Word
Logical AND Registers
Logical AND Register and Constant
Logical OR Registers
Rd Rd + Rr + C
Rdh:Rdl Rdh:Rdl + K
Rd Rd - Rr
SUBI
SBC
Rd Rd - K
Rd Rd - Rr - C
Rd Rd - K - C
Rdh:Rdl Rdh:Rdl - K
Rd Rd Rr
SBCI
SBIW
AND
ANDI
OR
Rd Rd K
Z, N, V
Rd Rd v Rr
Z, N, V
ORI
Logical OR Register and Constant
Exclusive OR Registers
One’s Complement
Rd Rd v K
Z, N, V
EOR
COM
NEG
SBR
Rd Rd Rr
Z, N, V
Rd 0xFF Rd
Rd 0x00 Rd
Rd Rd v K
Z, C, N, V
Z, C, N, V, H
Z, N, V
Rd
Two’s Complement
Rd,K
Rd,K
Rd
Set Bit(s) in Register
CBR
Clear Bit(s) in Register
Increment
Rd Rd (0xFF - K)
Rd Rd + 1
Z, N, V
INC
Z, N, V
DEC
Rd
Decrement
Rd Rd 1
Z, N, V
TST
Rd
Test for Zero or Minus
Rd Rd Rd
Z, N, V
CLR
Rd
Clear Register
Rd Rd Rd
Z, N, V
SER
Rd
Set Register
Rd 0xFF
None
MUL
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Multiply Unsigned
R1:R0 Rd x Rr
R1:R0 Rd x Rr
R1:R0 Rd x Rr
R1:R0 (Rd x Rr) << 1
R1:R0 (Rd x Rr) << 1
R1:R0 (Rd x Rr) << 1
Z, C
MULS
MULSU
FMUL
FMULS
FMULSU
Multiply Signed
Z, C
Multiply Signed with Unsigned
Fractional Multiply Unsigned
Fractional Multiply Signed
Fractional Multiply Signed with Unsigned
Z, C
Z, C
Z, C
Z, C
BRANCH INSTRUCTIONS
RJMP
IJMP
k
Relative Jump
PC PC + k + 1
None
None
2
2
Indirect Jump to (Z)
PC Z
RCALL
ICALL
RET
k
Relative Subroutine Call
Indirect Call to (Z)
PC PC + k + 1
None
None
3
PC Z
3
Subroutine Return
PC STACK
None
4
RETI
Interrupt Return
PC STACK
I
4
CPSE
CP
Rd,Rr
Compare, Skip if Equal
Compare
if (Rd = Rr) PC PC + 2 or 3
Rd Rr
None
1 / 2 / 3
1
Rd,Rr
Z, N, V, C, H
Z, N, V, C, H
Z, N, V, C, H
None
CPC
Rd,Rr
Compare with Carry
Rd Rr C
1
CPI
Rd,K
Compare Register with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register is Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register is Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Rd K
1
SBRC
SBRS
SBIC
Rr, b
if (Rr(b)=0) PC PC + 2 or 3
if (Rr(b)=1) PC PC + 2 or 3
if (P(b)=0) PC PC + 2 or 3
if (P(b)=1) PC PC + 2 or 3
if (SREG(s) = 1) then PCPC+k + 1
if (SREG(s) = 0) then PCPC+k + 1
if (Z = 1) then PC PC + k + 1
if (Z = 0) then PC PC + k + 1
if (C = 1) then PC PC + k + 1
if (C = 0) then PC PC + k + 1
if (C = 0) then PC PC + k + 1
if (C = 1) then PC PC + k + 1
if (N = 1) then PC PC + k + 1
if (N = 0) then PC PC + k + 1
if (N V= 0) then PC PC + k + 1
if (N V= 1) then PC PC + k + 1
if (H = 1) then PC PC + k + 1
if (H = 0) then PC PC + k + 1
if (T = 1) then PC PC + k + 1
if (T = 0) then PC PC + k + 1
if (V = 1) then PC PC + k + 1
if (V = 0) then PC PC + k + 1
1 / 2 / 3
1 / 2 / 3
1 / 2 / 3
1 / 2 / 3
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
Rr, b
None
P, b
P, b
s, k
s, k
k
None
SBIS
None
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
BRTS
BRTC
BRVS
BRVC
None
None
None
k
Branch if Not Equal
None
k
Branch if Carry Set
None
k
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
None
k
None
k
None
k
Branch if Minus
None
k
Branch if Plus
None
k
Branch if Greater or Equal, Signed
Branch if Less Than Zero, Signed
Branch if Half Carry Flag Set
Branch if Half Carry Flag Cleared
Branch if T Flag Set
None
k
None
k
None
k
None
k
None
k
Branch if T Flag Cleared
Branch if Overflow Flag is Set
Branch if Overflow Flag is Cleared
None
k
None
k
None
311
2486AA–AVR–02/2013
ATMEL [ ATMEL ]
