ATmega8(L)
The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conver-
sion and 13.5 ADC clock cycles after the start of an first conversion. When a conversion is
complete, the result is written to the ADC Data Registers, and ADIF is set. In single conversion
mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new
conversion will be initiated on the first rising ADC clock edge.
In Free Running mode, a new conversion will be started immediately after the conversion com-
pletes, while ADSC remains high. For a summary of conversion times, see Table 73 on page
193.
Figure 92. ADC Timing Diagram, First Conversion (Single Conversion Mode)
Next
First Conversion
Conversion
Cycle Number
1
2
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
ADC Clock
ADEN
ADSC
ADIF
MSB of Result
LSB of Result
ADCH
ADCL
MUX and REFS
Update
Conversion
Complete
MUX and REFS
Update
Sample & Hold
Figure 93. ADC Timing Diagram, Single Conversion
One Conversion
Next Conversion
1
2
3
4
5
6
7
8
9
10
11
12
13
1
2
3
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
MSB of Result
LSB of Result
ADCL
Sample & Hold
Conversion
Complete
MUX and REFS
Update
MUX and REFS
Update
192
2486AA–AVR–02/2013
ATMEL [ ATMEL ]
