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ATMEGA8L-8MUR 参数 Datasheet PDF下载

ATMEGA8L-8MUR图片预览
型号: ATMEGA8L-8MUR
PDF下载: 下载PDF文件 查看货源
内容描述: 8位爱特梅尔带有8K字节的系统内可编程闪存 [8-bit Atmel with 8KBytes In-System PRogrammable Flash]
分类和应用: 闪存微控制器和处理器外围集成电路异步传输模式PCATM时钟
文件页数/大小: 331 页 / 6705 K
品牌: ATMEL [ ATMEL ]
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ATmega8(L)  
Data Packet Format  
All data packets transmitted on the TWI bus are nine bits long, consisting of one data byte and  
an acknowledge bit. During a data transfer, the Master generates the clock and the START and  
STOP conditions, while the Receiver is responsible for acknowledging the reception. An  
Acknowledge (ACK) is signalled by the Receiver pulling the SDA line low during the ninth SCL  
cycle. If the Receiver leaves the SDA line high, a NACK is signalled. When the Receiver has  
received the last byte, or for some reason cannot receive any more bytes, it should inform the  
Transmitter by sending a NACK after the final byte. The MSB of the data byte is transmitted first.  
Figure 72. Data Packet Format  
Data MSB  
Data LSB  
ACK  
Aggregate  
SDA  
SDA from  
Transmitter  
SDA from  
Receiver  
SCL from  
Master  
1
2
7
8
9
STOP, REPEATED  
START or Next  
Data Byte  
SLA+R/W  
Data Byte  
Combining Address  
A transmission basically consists of a START condition, a SLA+R/W, one or more data packets  
and Data Packets into and a STOP condition. An empty message, consisting of a START followed by a STOP condi-  
a Transmission  
tion, is illegal. Note that the Wired-ANDing of the SCL line can be used to implement  
handshaking between the Master and the Slave. The Slave can extend the SCL low period by  
pulling the SCL line low. This is useful if the clock speed set up by the Master is too fast for the  
Slave, or the Slave needs extra time for processing between the data transmissions. The Slave  
extending the SCL low period will not affect the SCL high period, which is determined by the  
Master. As a consequence, the Slave can reduce the TWI data transfer speed by prolonging the  
SCL duty cycle.  
Figure 73 shows a typical data transmission. Note that several data bytes can be transmitted  
between the SLA+R/W and the STOP condition, depending on the software protocol imple-  
mented by the application software.  
Figure 73. Typical Data Transmission  
Addr MSB  
Addr LSB R/W  
ACK  
Data MSB  
Data LSB ACK  
SDA  
SCL  
1
2
7
8
9
1
2
7
8
9
START  
SLA+R/W  
Data Byte  
STOP  
160  
2486AA–AVR–02/2013  
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