ATmega8(L)
the figure. The clock recovery logic then uses samples 8, 9 and 10 for Normal mode, and
samples 4, 5 and 6 for Double Speed mode (indicated with sample numbers inside boxes on the
figure), to decide if a valid start bit is received. If two or more of these three samples have logical
high levels (the majority wins), the start bit is rejected as a noise spike and the Receiver starts
looking for the next high to low-transition. If however, a valid start bit is detected, the clock
recovery logic is synchronized and the data recovery can begin. The synchronization process is
repeated for each start bit.
Asynchronous Data
Recovery
When the Receiver clock is synchronized to the start bit, the data recovery can begin. The data
recovery unit uses a state machine that has 16 states for each bit in Normal mode and eight
states for each bit in Double Speed mode. Figure 66 shows the sampling of the data bits and the
parity bit. Each of the samples is given a number that is equal to the state of the recovery unit.
Figure 66. Sampling of Data and Parity Bit
RxD
BIT n
Sample
(U2X = 0)
1
1
2
3
2
4
5
3
6
7
4
8
9
5
10
11
6
12
13
7
14
15
8
16
1
1
Sample
(U2X = 1)
The decision of the logic level of the received bit is taken by doing a majority voting of the logic
value to the three samples in the center of the received bit. The center samples are emphasized
on the figure by having the sample number inside boxes. The majority voting process is done as
follows: If two or all three samples have high levels, the received bit is registered to be a logic 1.
If two or all three samples have low levels, the received bit is registered to be a logic 0. This
majority voting process acts as a low pass filter for the incoming signal on the RxD pin. The
recovery process is then repeated until a complete frame is received. Including the first stop bit.
Note that the Receiver only uses the first stop bit of a frame.
Figure 67 shows the sampling of the stop bit and the earliest possible beginning of the start bit of
the next frame.
Figure 67. Stop Bit Sampling and Next Start Bit Sampling
(A)
(B)
(C)
RxD
STOP 1
Sample
(U2X = 0)
1
1
2
3
2
4
5
3
6
7
4
8
9
5
10
0/1 0/1 0/1
Sample
(U2X = 1)
6
0/1
The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop
bit is registered to have a logic 0 value, the Frame Error (FE) Flag will be set.
A new high to low transition indicating the start bit of a new frame can come right after the last of
the bits used for majority voting. For Normal Speed mode, the first low level sample can be at
point marked (A) in Figure 67. For Double Speed mode the first low level must be delayed to (B).
(C) marks a stop bit of full length. The early start bit detection influences the operational range of
the Receiver.
143
2486AA–AVR–02/2013
ATMEL [ ATMEL ]
