ATmega8(L)
Table 42. Waveform Generation Mode Bit Description
WGM21 WGM20 Timer/Counter Mode
(CTC2)
Update of TOV2 Flag
OCR2 Set
Mode
(PWM2) of Operation(1)
TOP
0xFF
0xFF
0
1
2
3
0
0
1
1
0
1
0
1
Normal
Immediate MAX
TOP BOTTOM
PWM, Phase Correct
CTC
OCR2 Immediate MAX
0xFF BOTTOM MAX
Fast PWM
Note:
1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions.
However, the functionality and location of these bits are compatible with previous versions of
the timer
• Bit 5:4 – COM21:0: Compare Match Output Mode
These bits control the Output Compare Pin (OC2) behavior. If one or both of the COM21:0 bits
are set, the OC2 output overrides the normal port functionality of the I/O pin it is connected to.
However, note that the Data Direction Register (DDR) bit corresponding to OC2 pin must be set
in order to enable the output driver.
When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0
bit setting.
Table 43 shows the COM21:0 bit functionality when the WGM21:0 bits are set to a normal or
CTC mode (non-PWM).
Table 43. Compare Output Mode, Non-PWM Mode
COM21
COM20
Description
0
0
1
1
0
1
0
1
Normal port operation, OC2 disconnected
Toggle OC2 on Compare Match
Clear OC2 on Compare Match
Set OC2 on Compare Match
Table 44 shows the COM21:0 bit functionality when the WGM21:0 bits are set to fast PWM
mode.
Table 44. Compare Output Mode, Fast PWM Mode(1)
COM21
COM20
Description
0
0
1
0
1
0
Normal port operation, OC2 disconnected
Reserved
Clear OC2 on Compare Match, set OC2 at BOTTOM,
(non-inverting mode)
1
1
Set OC2 on Compare Match, clear OC2 at BOTTOM,
(inverting mode)
Note:
1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the Compare
Match is ignored, but the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 110
for more details
115
2486AA–AVR–02/2013
ATMEL [ ATMEL ]
