ATmega8(L)
goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indi-
cated by the two arrows t
pd,max
and t
pd,min
, a single signal transition on the pin will be delayed
between ½ and 1-½ system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a
nop
instruction must be inserted as indi-
cated in
The
out
instruction sets the “SYNC LATCH” signal at the positive edge of the
clock. In this case, the delay t
pd
through the synchronizer is 1 system clock period.
Figure 24.
Synchronization when Reading a Software Assigned Pin Value
SYSTEM CLK
r16
INSTRUCTIONS
SYNC LATCH
PINxn
r17
0x00
t
pd
0xFF
out PORTx, r16
nop
0xFF
in r17, PINx
54
2486AA–AVR–02/2013
ATMEL [ ATMEL CORPORATION ]
