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ATMEGA8L-8AUR 参数 Datasheet PDF下载

ATMEGA8L-8AUR图片预览
型号: ATMEGA8L-8AUR
PDF下载: 下载PDF文件 查看货源
内容描述: 8位爱特梅尔带有8K字节的系统内可编程闪存 [8-bit Atmel with 8KBytes In-System PRogrammable Flash]
分类和应用: 闪存
文件页数/大小: 331 页 / 6705 K
品牌: ATMEL [ ATMEL ]
 浏览型号ATMEGA8L-8AUR的Datasheet PDF文件第49页浏览型号ATMEGA8L-8AUR的Datasheet PDF文件第50页浏览型号ATMEGA8L-8AUR的Datasheet PDF文件第51页浏览型号ATMEGA8L-8AUR的Datasheet PDF文件第52页浏览型号ATMEGA8L-8AUR的Datasheet PDF文件第54页浏览型号ATMEGA8L-8AUR的Datasheet PDF文件第55页浏览型号ATMEGA8L-8AUR的Datasheet PDF文件第56页浏览型号ATMEGA8L-8AUR的Datasheet PDF文件第57页  
ATmega8(L)  
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn}  
= 0b11), an intermediate state with either pull-up enabled ({DDxn, PORTxn} = 0b01) or output  
low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully accept-  
able, as a high-impedant environment will not notice the difference between a strong high driver  
and a pull-up. If this is not the case, the PUD bit in the SFIOR Register can be set to disable all  
pull-ups in all ports.  
Switching between input with pull-up and output low generates the same problem. The user  
must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn}  
= 0b11) as an intermediate step.  
Table 20 summarizes the control signals for the pin value.  
Table 20. Port Pin Configurations  
PUD  
DDxn PORTxn (in SFIOR)  
I/O  
Pull-up Comment  
0
0
0
1
X
0
Input  
No  
Tri-state (Hi-Z)  
Pxn will source current if external  
pulled low.  
Input  
Yes  
0
1
1
1
0
1
1
X
X
Input  
No  
No  
No  
Tri-state (Hi-Z)  
Output  
Output  
Output Low (Sink)  
Output High (Source)  
Reading the Pin Value Independent of the setting of Data Direction bit DDxn, the port pin can be read through the  
PINxn Register Bit. As shown in Figure 22 on page 52, the PINxn Register bit and the preceding  
latch constitute a synchronizer. This is needed to avoid metastability if the physical pin changes  
value near the edge of the internal clock, but it also introduces a delay. Figure 23 shows a timing  
diagram of the synchronization when reading an externally applied pin value. The maximum and  
minimum propagation delays are denoted tpd,max and tpd,min, respectively.  
Figure 23. Synchronization when Reading an Externally Applied Pin Value  
SYSTEM CLK  
XXX  
XXX  
in r17, PINx  
INSTRUCTIONS  
SYNC LATCH  
PINxn  
0x00  
tpd, max  
0xFF  
r17  
tpd, min  
Consider the clock period starting shortly after the first falling edge of the system clock. The latch  
is closed when the clock is low, and goes transparent when the clock is high, as indicated by the  
shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock  
53  
2486AA–AVR–02/2013