2.3.7
2.3.8
Port E (PE7:PE0)
Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buf-
fers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are
externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
Port E also serves the functions of various special features of the ATmega64A as listed on page 80.
Port F (PF7:PF0)
Port F serves as the analog inputs to the A/D Converter.
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal
pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both
high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not
running. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS) and PF4(TCK) will be
activated even if a reset occurs.
The TDO pin is tri-stated unless TAP states that shift out data are entered.
Port F also serves the functions of the JTAG interface.
In ATmega103 compatibility mode, Port F is an input port only.
2.3.9
Port G (PG4:PG0)
Port G is a 5-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port G output buf-
fers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are
externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
Port G also serves the functions of various special features.
In ATmega103 compatibility mode, these pins only serves as strobes signals to the external memory as well as
input to the 32 kHz Oscillator, and the pins are initialized to PG0 = 1, PG1 = 1, and PG2 = 0 asynchronously when
a reset condition becomes active, even if the clock is not running. PG3 and PG4 are Oscillator pins.
2.3.10
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock
is not running. The minimum pulse length is given in Table 29-3 on page 307. Shorter pulses are not guaranteed to
generate a reset.
2.3.11
2.3.12
2.3.13
XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting Oscillator amplifier.
AVCC
AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to VCC, even if
the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter.
2.3.14
AREF
AREF is the analog reference pin for the A/D Converter.
ATmega64A [DATASHEET]
6
8160DS–AVR–02/2013
ATMEL [ ATMEL ]
