compliant JTAG test interface, also used for accessing the On-chip Debug system and programming, and six soft-
ware selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters,
SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but
freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save
mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the
device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer
and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator
is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consump-
tion. In Extended Standby mode, both the main Oscillator and the asynchronous timer continue to run.
The device is manufactured using Atmel’s high-density non-volatile memory technology. The On-chip ISP Flash
allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional non-
volatile memory programmer, or by an On-chip Boot program running on the AVR core. The Boot Program can use
any interface to download the Application Program in the Application Flash memory. Software in the Boot Flash
section will continue to run while the Application Flash section is updated, providing true Read-While-Write opera-
tion. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel
ATmega64A is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embed-
ded control applications.
The ATmega64A AVR is supported with a full suite of program and system development tools including: C compil-
ers, macro assemblers, program debugger/simulators, In-Circuit Emulators, and evaluation kits.
2.2
ATmega103 and ATmega64A Compatibility
The ATmega64A is a highly complex microcontroller where the number of I/O locations supersedes the 64 I/O
location reserved in the AVR instruction set. To ensure backward compatibility with the ATmega103, all I/O loca-
tions present in ATmega103 have the same location in ATmega64A. Most additional I/O locations are added in an
Extended I/O space starting from 0x60 to 0xFF (that is, in the ATmega103 internal RAM space). These location
can be reached by using LD/LDS/LDD and ST/STS/STD instructions only, not by using IN and OUT instructions.
The relocation of the internal RAM space may still be a problem for ATmega103 users. Also, the increased number
of Interrupt Vectors might be a problem if the code uses absolute addresses. To solve these problems, an
ATmega103 compatibility mode can be selected by programming the fuse M103C. In this mode, none of the func-
tions in the Extended I/O space are in use, so the internal RAM is located as in ATmega103. Also, the extended
Interrupt Vectors are removed.
The ATmega64A is 100% pin compatible with ATmega103, and can replace the ATmega103 on current printed cir-
cuit boards. The application notes “Replacing ATmega103 by ATmega128” and “Migration between ATmega64
and ATmega128” describes what the user should be aware of replacing the ATmega103 by an ATmega128 or
ATmega64.
2.2.1
ATmega103 Compatibility Mode
By programming the M103C Fuse, the ATmega64A will be compatible with the ATmega103 regards to RAM, I/O
pins and Interrupt Vectors as described above. However, some new features in ATmega64A are not available in
this compatibility mode, these features are listed below:
• One USART instead of two, asynchronous mode only. Only the eight least significant bits of the Baud Rate
Register is available.
• One 16-bits Timer/Counter with two compare registers instead of two 16-bits Timer/Counters with three
compare registers.
• Two-wire serial interface is not supported.
• Port G serves alternate functions only (not a general I/O port).
• Port F serves as digital input only in addition to analog input to the ADC.
ATmega64A [DATASHEET]
8160DS–AVR–02/2013
4
ATMEL [ ATMEL CORPORATION ]
