ATmega48/88/168
AVR
This section describes the different memories in the ATmega48/88/168. The AVR archi-
tecture has two main memory spaces, the Data Memory and the Program Memory
space. In addition, the ATmega48/88/168 features an EEPROM Memory for data stor-
age. All three memory spaces are linear and regular.
ATmega48/88/168
Memories
In-System
Reprogrammable Flash
Program Memory
The ATmega48/88/168 contains 4/8/16K bytes On-chip In-System Reprogrammable
Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide,
the Flash is organized as 2/4/8K x 16. For software security, the Flash Program memory
space is divided into two sections, Boot Loader Section and Application Program Sec-
tion in ATmega88 and ATmega168. ATmega48 does not have separate Boot Loader
and Application Program sections, and the SPM instruction can be executed from the
entire Flash. See SELFPRGEN description in section “Store Program Memory Control
and Status Register – SPMCSR” on page 250 and page 260for more details.
The Flash memory has an endurance of at least 10,000 write/erase cycles. The
ATmega48/88/168 Program Counter (PC) is 11/12/13 bits wide, thus addressing the
2/4/8K program memory locations. The operation of Boot Program section and associ-
ated Boot Lock bits for software protection are described in detail in “Self-Programming
the Flash, ATmega48” on page 248 and “Boot Loader Support – Read-While-Write Self-
Programming, ATmega88 and ATmega168” on page 255. “Memory Programming” on
page 270 contains a detailed description on Flash Programming in SPI- or Parallel Pro-
gramming mode.
Constant tables can be allocated within the entire program memory address space (see
the LPM – Load Program Memory instruction description).
Timing diagrams for instruction fetch and execution are presented in “Instruction Execu-
tion Timing” on page 12.
Figure 8. Program Memory Map, ATmega48
Program Memory
0x0000
Application Flash Section
0x7FF
15
2545D–AVR–07/04
ATMEL [ ATMEL ]
