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ATMEGA32L-8AUR 参数 Datasheet PDF下载

ATMEGA32L-8AUR图片预览
型号: ATMEGA32L-8AUR
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 8MHz, CMOS, PQFP44, 10 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, GREEN, PLASTIC, MS-026ACB, TQFP-44]
分类和应用: 闪存微控制器
文件页数/大小: 347 页 / 3171 K
品牌: ATMEL [ ATMEL ]
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PROG_COMMANDS ($5)  
The AVR specific public JTAG instruction for entering programming commands via the  
JTAG port. The 15-bit Programming Command Register is selected as Data Register.  
The active states are the following:  
Capture-DR: The result of the previous command is loaded into the Data Register.  
Shift-DR: The Data Register is shifted by the TCK input, shifting out the result of the  
previous command and shifting in the new command.  
Update-DR: The programming command is applied to the Flash inputs  
Run-Test/Idle: One clock cycle is generated, executing the applied command (not  
always required, see Table 116 below).  
PROG_PAGELOAD ($6)  
The AVR specific public JTAG instruction to directly load the Flash data page via the  
JTAG port. The 1024 bit Virtual Flash Page Load Register is selected as Data Register.  
This is a virtual scan chain with length equal to the number of bits in one Flash page.  
Internally the Shift Register is 8-bit. Unlike most JTAG instructions, the Update-DR state  
is not used to transfer data from the Shift Register. The data are automatically trans-  
ferred to the Flash page buffer byte by byte in the Shift-DR state by an internal state  
machine. This is the only active state:  
Shift-DR: Flash page data are shifted in from TDI by the TCK input, and  
automatically loaded into the Flash page one byte at a time.  
Note:  
The JTAG instruction PROG_PAGELOAD can only be used if the AVR device is the first  
device in JTAG scan chain. If the AVR cannot be the first device in the scan chain, the  
byte-wise programming algorithm must be used.  
PROG_PAGEREAD ($7)  
The AVR specific public JTAG instruction to read one full Flash data page via the JTAG  
port. The 1032 bit Virtual Flash Page Read Register is selected as Data Register. This is  
a virtual scan chain with length equal to the number of bits in one Flash page plus 8.  
Internally the Shift Register is 8-bit. Unlike most JTAG instructions, the Capture-DR  
state is not used to transfer data to the Shift Register. The data are automatically trans-  
ferred from the Flash page buffer byte by byte in the Shift-DR state by an internal state  
machine. This is the only active state:  
Shift-DR: Flash data are automatically read one byte at a time and shifted out on  
TDO by the TCK input. The TDI input is ignored.  
Note:  
The JTAG instruction PROG_PAGEREAD can only be used if the AVR device is the first  
device in JTAG scan chain. If the AVR cannot be the first device in the scan chain, the  
byte-wise programming algorithm must be used.  
Data Registers  
The Data Registers are selected by the JTAG Instruction Registers described in section  
“Programming Specific JTAG Instructions” on page 274. The Data Registers relevant for  
programming operations are:  
Reset Register  
Programming Enable Register  
Programming Command Register  
Virtual Flash Page Load Register  
Virtual Flash Page Read Register  
276  
ATmega32(L)  
2503J–AVR–10/06  
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