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ATMEGA32L-8PL 参数 Datasheet PDF下载

ATMEGA32L-8PL图片预览
型号: ATMEGA32L-8PL
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, 8MHz, CMOS, PDIP40, 0.600 INCH, PLASTIC, MS-011AC, DIP-40]
分类和应用: 闪存微控制器
文件页数/大小: 347 页 / 3171 K
品牌: ATMEL [ ATMEL ]
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AVR CPU Core  
Introduction  
This section discusses the AVR core architecture in general. The main function of the  
CPU core is to ensure correct program execution. The CPU must therefore be able to  
access memories, perform calculations, control peripherals, and handle interrupts.  
Architectural Overview  
Figure 3. Block Diagram of the AVR MCU Architecture  
Data Bus 8-bit  
Program  
Counter  
Status  
and Control  
Flash  
Program  
Memory  
Interrupt  
Unit  
32 x 8  
General  
Purpose  
Registrers  
Instruction  
Register  
SPI  
Unit  
Instruction  
Decoder  
Watchdog  
Timer  
ALU  
Analog  
Comparator  
Control Lines  
I/O Module1  
I/O Module 2  
I/O Module n  
Data  
SRAM  
EEPROM  
I/O Lines  
In order to maximize performance and parallelism, the AVR uses a Harvard architecture  
– with separate memories and buses for program and data. Instructions in the program  
memory are executed with a single level pipelining. While one instruction is being exe-  
cuted, the next instruction is pre-fetched from the program memory. This concept  
enables instructions to be executed in every clock cycle. The program memory is In-  
System Reprogrammable Flash memory.  
The fast-access Register File contains 32 x 8-bit general purpose working registers with  
a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU)  
operation. In a typical ALU operation, two operands are output from the Register File,  
the operation is executed, and the result is stored back in the Register File – in one  
clock cycle.  
Six of the 32 registers can be used as three 16-bit indirect address register pointers for  
Data Space addressing – enabling efficient address calculations. One of the these  
address pointers can also be used as an address pointer for look up tables in Flash Pro-  
gram memory. These added function registers are the 16-bit X-, Y-, and Z-register,  
described later in this section.  
The ALU supports arithmetic and logic operations between registers or between a con-  
stant and a register. Single register operations can also be executed in the ALU. After  
8
ATmega32(L)  
2503J–AVR–10/06  
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