succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a
single signal transition on the pin will be delayed between ½ and 1½ system clock
period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as
indicated in Figure 25. The out instruction sets the “SYNC LATCH” signal at the positive
edge of the clock. In this case, the delay tpd through the synchronizer is one system
clock period.
Figure 25. Synchronization when Reading a Software Assigned Pin Value
SYSTEM CLK
r16
0xFF
nop
in r17, PINx
out PORTx, r16
INSTRUCTIONS
SYNC LATCH
PINxn
0xFF
0x00
tpd
r17
52
ATmega32(L)
2503J–AVR–10/06
ATMEL [ ATMEL ]
