ATmega16(L)
enabled state is fully acceptable, as a high-impedant environment will not notice the dif-
ference between a strong high driver and a pull-up. If this is not the case, the PUD bit in
the SFIOR Register can be set to disable all pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The
user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state
({DDxn, PORTxn} = 0b11) as an intermediate step.
Table 20 summarizes the control signals for the pin value.
Table 20. Port Pin Configurations
PUD
DDxn PORTxn (in SFIOR)
I/O
Pull-up Comment
0
0
X
Input
No
Tri-state (Hi-Z)
Pxn will source current if ext. pulled
low.
0
0
1
1
1
1
0
1
0
1
Input
Input
Yes
No
No
No
Tri-state (Hi-Z)
X
X
Output
Output
Output Low (Sink)
Output High (Source)
Reading the Pin Value
Independent of the setting of Data Direction bit DDxn, the port pin can be read through
the PINxn Register bit. As shown in Figure 23, the PINxn Register bit and the preceding
latch constitute a synchronizer. This is needed to avoid metastability if the physical pin
changes value near the edge of the internal clock, but it also introduces a delay. Figure
24 shows a timing diagram of the synchronization when reading an externally applied
pin value. The maximum and minimum propagation delays are denoted tpd,max and tpd,min
respectively.
Figure 24. Synchronization when Reading an Externally Applied Pin Value
SYSTEM CLK
in r17, PINx
XXX
XXX
INSTRUCTIONS
SYNC LATCH
PINxn
0xFF
r17
0x00
t
pd, max
t
pd, min
Consider the clock period starting shortly after the first falling edge of the system clock.
The latch is closed when the clock is low, and goes transparent when the clock is high,
as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is
latched when the system clock goes low. It is clocked into the PINxn Register at the
49
2466E–AVR–10/02
ATMEL [ ATMEL ]
