ATmega8U2/16U2/32U2
12.4 Register Description for I/O-Ports
12.4.1
MCUCR – MCU Control Register
Bit
7
6
–
5
–
4
3
–
2
–
1
IVSEL
R/W
0
0
IVCE
R/W
0
0x35 (0x55)
Read/Write
Initial Value
JTD
R/W
0
PUD
R/W
0
MCUCR
R
0
R
0
R
0
R
0
• Bit 4 – PUD: Pull-up Disable
When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and
PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Con-
figuring the Pin” on page 68 for more details about this feature.
12.4.2
12.4.3
12.4.4
12.4.5
12.4.6
12.4.7
PORTB – Port B Data Register
Bit
7
6
PORTB6
R/W
5
PORTB5
R/W
4
PORTB4
R/W
3
PORTB3
R/W
2
PORTB2
R/W
1
PORTB1
R/W
0
PORTB0
R/W
0x05 (0x25)
Read/Write
Initial Value
PORTB7
PORTB
DDRB
PINB
R/W
0
0
0
0
0
0
0
0
DDRB – Port B Data Direction Register
Bit
7
DDB7
R/W
0
6
DDB6
R/W
0
5
DDB5
R/W
0
4
DDB4
R/W
0
3
DDB3
R/W
0
2
DDB2
R/W
0
1
DDB1
R/W
0
0
DDB0
R/W
0
0x04 (0x24)
Read/Write
Initial Value
PINB – Port B Input Pins Address
Bit
7
6
5
4
3
2
1
0
0x03 (0x23)
Read/Write
Initial Value
PINB7
R/W
N/A
PINB6
R/W
N/A
PINB5
R/W
N/A
PINB4
R/W
N/A
PINB3
R/W
N/A
PINB2
R/W
N/A
PINB1
R/W
N/A
PINB0
R/W
N/A
PORTC – Port C Data Register
Bit
7
6
PORTC6
R/W
5
PORTC5
R/W
4
PORTC4
R/W
3
-
2
PORTC2
R/W
1
PORTC1
R/W
0
PORTC0
R/W
0x08 (0x28)
Read/Write
Initial Value
PORTC7
PORTC
DDRC
PINC
R/W
0
R
0
0
0
0
0
0
0
DDRC – Port C Data Direction Register
Bit
7
DDC7
R/W
0
6
DDC6
R/W
0
5
DDC5
R/W
0
4
DDC4
R/W
0
3
-
2
DDC2
R/W
0
1
DDC1
R/W
0
0
DDC0
R/W
0
0x07 (0x27)
Read/Write
Initial Value
R
0
PINC – Port C Input Pins Address
Bit
7
6
5
4
3
-
2
1
0
0x06 (0x26)
Read/Write
Initial Value
PINC7
R/W
N/A
PINC6
R/W
N/A
PINC5
R/W
N/A
PINC4
R/W
N/A
PINC2
R/W
N/A
PINC1
R/W
N/A
PINC0
R/W
N/A
R
N/A
82
7799D–AVR–11/10
ATMEL [ ATMEL ]
