ATmega8U2/16U2/32U2
Table 12-10. Overriding Signals for Alternate Functions PD7..PD4
PD7/T0/INT7/
HBW/CTS
PD6/INT6/
RTS
Signal Name
PD5/XCK/PCINT12
PD4/INT5
PUOE
CTS
RTS
0
0
0
PORTD7 •
PUD
PUOV
0
0
DDOE
DDOV
CTS
0
RTS
1
0
0
0
0
RTS
PVOE
PVOV
0
0
OUTPUT
ENABLE
XCK OUTPUT ENABLE
XCK1 OUTPUT
0
0
RTS
OUTPUT
INT7/CTS
ENABLE
INT6
ENABLE
INT5
ENABLE
DIEOE
DIEOV
PCINT12 ENABLE
1
1
1
1
T0 INPUT
XCK INPUT
DI
INT7 INPUT
CTS INPUT
INT6 INPUT
–
INT5 INPUT
–
PCINT12 INPUT
AIO
–
–
Table 12-11. Overriding Signals for Alternate Functions in PD3..PD0(1)
PD2/INT2/RXD1/
Signal Name
PUOE
PD3/INT3/TXD1
AIN1
PD1/INT1/AIN0
PD0/INT0/OC0B
TXEN1
0
RXEN1
0
0
0
0
0
0
0
PUOV
PORTD2 • PUD
0
DDOE
TXEN1
1
RXEN1
0
DDOV
0
0
0
0
PVOE
TXEN1
TXD1
OC0B ENABLE
OC0B
PVOV
INT2 ENABLE
AIN1 ENABLE
INT1 ENABLE
AIN0 ENABLE
DIEOE
INT3 ENABLE
INT0 ENABLE
DIEOV
DI
1
AIN1 ENABLE
INT2 INPUT/RXD1
AIN1 INPUT
AIN0 ENABLE
INT1 INPUT
AIN0 INPUT
1
INT3 INPUT
–
INT0 INPUT
–
AIO
Note:
1. When enabled, the 2-wire Serial Interface enables Slew-Rate controls on the output pins PD0
and PD1. This is not shown in this table. In addition, spike filters are connected between the
AIO outputs shown in the port figure.
81
7799D–AVR–11/10
ATMEL [ ATMEL ]
