ATmega8U2/16U2/32U2
Table 26-7. SPI Interface Timing Requirements (Slave Mode)
SS
10
16
9
SCK
(CPOL = 0)
11
11
SCK
(CPOL = 1)
13
14
12
MOSI
(Data Input)
MSB
...
LSB
15
17
MISO
(Data Output)
MSB
...
LSB
X
26.8 Hardware Boot EntranceTiming Characteristics
Figure 26-4. Hardware Boot Timing Requirements
RESET
tSHRH
tHHRH
ALE/HWB
Table 26-8. Hardware Boot Timings
Symbol
Parameter
Min
Max
HWB low Setup before Reset High
0
tSHRH
StartUpTime(SUT) +
HWB low Hold after Reset High
tHHRH
Time Out Delay(TOUT)
26.9 Parallel Programming Characteristics
Figure 26-5. Parallel Programming Timing, Including some General Timing Requirements
tXLWL
tXHXL
XTAL1
tDVXH
tXLDX
Data & Contol
(DATA, XA0/1, BS1, BS2)
tBVPH
tPLBX tBVWL
tWLBX
PAGEL
tPHPL
tWLWH
WR
tPLWL
WLRL
RDY/BSY
tWLRH
270
7799D–AVR–11/10
ATMEL [ ATMEL ]
