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ATMEGA16U2-MUR 参数 Datasheet PDF下载

ATMEGA16U2-MUR图片预览
型号: ATMEGA16U2-MUR
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器具有ISP功能的Flash 8/16 / 32K Butes [8-bit Microcontroller with 8/16/32K Butes of ISP Flash]
分类和应用: 微控制器异步传输模式PCATM
文件页数/大小: 310 页 / 4432 K
品牌: ATMEL [ ATMEL ]
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ATmega8U2/16U2/32U2  
19.7.4  
UCSRnC – USART MSPIM Control and Status Register n C  
Bit  
7
UMSELn1  
R/W  
6
UMSELn0  
R/W  
5
4
3
2
UDORDn  
R/W  
1
UCPHAn  
R/W  
0
UCPOLn  
R/W  
UCSRnC  
Read/Write  
Initial Value  
R
0
R
0
R
0
0
0
1
1
0
• Bit 7:6 - UMSELn[1:0]: USART Mode Select  
These bits select the mode of operation of the USART as shown in Table 19-3. See “UCSRnC –  
USART Control and Status Register n C” on page 169 for full description of the normal USART  
operation. The MSPIM is enabled when both UMSELn bits are set to one. The UDORDn,  
UCPHAn, and UCPOLn can be set in the same write operation where the MSPIM is enabled.  
Table 19-3. UMSELn Bits Settings  
UMSELn1  
UMSELn0  
Mode  
0
0
1
1
0
1
0
1
Asynchronous USART  
Synchronous USART  
(Reserved)  
Master SPI (MSPIM)  
• Bit 5:3 - Reserved Bits in MSPI mode  
When in MSPI mode, these bits are reserved for future use. For compatibility with future devices,  
these bits must be written to zero when UCSRnC is written.  
• Bit 2 - UDORDn: Data Order  
When set to one the LSB of the data word is transmitted first. When set to zero the MSB of the  
data word is transmitted first. Refer to the Frame Formats section page 4 for details.  
• Bit 1 - UCPHAn: Clock Phase  
The UCPHAn bit setting determine if data is sampled on the leasing edge (first) or tailing (last)  
edge of XCKn. Refer to the SPI Data Modes and Timing section page 4 for details.  
• Bit 0 - UCPOLn: Clock Polarity  
The UCPOLn bit sets the polarity of the XCKn clock. The combination of the UCPOLn and  
UCPHAn bit settings determine the timing of the data transfer. Refer to the SPI Data Modes and  
Timing section page 4 for details.  
19.7.5  
UBRRnL and UBRRnH – USART MSPIM Baud Rate Registers  
The function and bit description of the baud rate registers in MSPI mode is identical to normal  
USART operation. See “UBRRnL and UBRRnH – USART Baud Rate Registers” on page 171.  
19.8 AVR USART MSPIM vs. AVR SPI  
The USART in MSPIM mode is fully compatible with the AVR SPI regarding:  
• Master mode timing diagram.  
• The UCPOLn bit functionality is identical to the SPI CPOL bit.  
• The UCPHAn bit functionality is identical to the SPI CPHA bit.  
• The UDORDn bit functionality is identical to the SPI DORD bit.  
183  
7799D–AVR–11/10  
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