ATmega8U2/16U2/32U2
stop sending characters. RTS usage and so associated flow control is enabled using RTSEN bit
in UCSRnD.
Figure 18-8. shows a reception example.
Figure 18-8. Reception Flow Control Waveform Example
FIFO
0
1
2
1
0
1
Index
RXD
RTS
CPU Read
C3
C1 C2
Figure 18-9. RTS behavior
Stop
Stop
Start
Byte0
Start
Byte1
Start
Byte2
RXD
1 additional byte may be sent
if the transmitter misses the RTS trig
RTS
Read from CPU
RTS will rise at 2/3 of the last received stop bit if the receive fifo is full.
To ensure reliable transmissions, even after a RTS rise, an extra-data can still be received and
stored in the Receive Shift Register.
18.10.2 Transmission Flow Control
The transmission flow can be controlled by hardware using the CTS pin controlled by the exter-
nal receiver. The aim of the flow control is to stop transmission when the receiver is full of data
(CTS = 1). CTS usage and so associated flow control is enabled using CTSEN bit in UCSRnD.
The CTS pin is sampled at each CPU write and at the middle of the last stop bit that is
curently being sent.
Figure 18-10. CTS behavior
Write from CPU
Stop
Stop
Start
Byte0
Start
Byte1
Start
Byte2
TXD
CTS
sample
sample
sample
166
7799D–AVR–11/10
ATMEL [ ATMEL ]
