ATmega169P
interrupt request even if INT0 is configured as an output. The corresponding interrupt of External
Interrupt Request 0 is executed from the INT0 Interrupt Vector.
11.2.3
EIFR – External Interrupt Flag Register
Bit
0x1C (0x3C)
7
6
5
–
4
–
3
–
2
–
1
–
0
INTF0
R/W
0
PCIF1
PCIF0
R/W
0
EIFR
Read/Write
Initial Value
R/W
0
R
0
R
0
R
0
R
0
R
0
• Bit 7 – PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1 becomes set
(one). If the I-bit in SREG and the PCIE1 bit in EIMSK are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
• Bit 6 – PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT7:0 pin triggers an interrupt request, PCIF0 becomes set
(one). If the I-bit in SREG and the PCIE0 bit in EIMSK are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
• Bit 0 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set
(one). If the I-bit in SREG and the INT0 bit in EIMSK are set (one), the MCU will jump to the cor-
responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared
when INT0 is configured as a level interrupt.
11.2.4
PCMSK1 – Pin Change Mask Register 1
Bit
7
6
PCINT14
R/W
0
5
PCINT13
R/W
0
4
PCINT12
R/W
0
3
PCINT11
R/W
0
2
PCINT10
R/W
0
1
PCINT9
R/W
0
0
PCINT8
R/W
0
PCINT15
R/W
0
PCMSK1
(0x6C)
Read/Write
Initial Value
• Bit 7:0 – PCINT15:8: Pin Change Enable Mask 15..8
Each PCINT15:8-bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT15:8 is set and the PCIE1 bit in EIMSK is set, pin change interrupt is enabled on the
corresponding I/O pin. If PCINT15..8 is cleared, pin change interrupt on the corresponding I/O
pin is disabled.
63
8018A–AVR–03/06
ATMEL [ ATMEL ]
