ATmega169P
22.4 LCD Usage .........................................................................................................240
22.5 LCD Register Description ...................................................................................244
23 JTAG Interface and On-chip Debug System ..................................... 250
23.1 Overview ............................................................................................................250
23.2 TAP – Test Access Port .....................................................................................251
23.3 TAP Controller ....................................................................................................253
23.4 Using the Boundary-scan Chain .........................................................................254
23.5 Using the On-chip Debug System ......................................................................254
23.6 On-chip Debug Specific JTAG Instructions ........................................................255
23.7 On-chip Debug Related Register in I/O Memory ................................................256
23.8 Using the JTAG Programming Capabilities ........................................................256
23.9 Bibliography ........................................................................................................256
24 IEEE 1149.1 (JTAG) Boundary-scan ................................................... 257
24.1 Features .............................................................................................................257
24.2 System Overview ...............................................................................................257
24.3 Data Registers ....................................................................................................258
24.4 Boundary-scan Specific JTAG Instructions ........................................................259
24.5 Boundary-scan Chain .........................................................................................261
24.6 Boundary-scan Order .........................................................................................271
24.7 Boundary-scan Description Language Files .......................................................277
24.8 Boundary-scan Related Register in I/O Memory ................................................278
25 Boot Loader Support – Read-While-Write Self-Programming ......... 279
25.1 Boot Loader Features .........................................................................................279
25.2 Application and Boot Loader Flash Sections ......................................................279
25.3 Read-While-Write and No Read-While-Write Flash Sections .............................280
25.4 Boot Loader Lock Bits ........................................................................................283
25.5 Entering the Boot Loader Program .....................................................................284
25.6 Addressing the Flash During Self-Programming ................................................285
25.7 Self-Programming the Flash ...............................................................................286
25.8 Register Description ...........................................................................................293
26 Memory Programming ......................................................................... 295
26.1 Program And Data Memory Lock Bits ................................................................295
26.2 Fuse Bits ............................................................................................................296
26.3 Signature Bytes ..................................................................................................298
26.4 Calibration Byte ..................................................................................................298
v
8018A–AVR–03/06
ATMEL [ ATMEL ]
