24.8 Boundary-scan Related Register in I/O Memory
24.8.1
MCUCR – MCU Control Register
The MCU Control Register contains control bits for general MCU functions.
Bit
7
6
-
5
-
4
3
–
2
–
1
IVSEL
R/W
0
0
IVCE
R/W
0
0x35 (0x55)
Read/Write
Initial Value
JTD
R/W
0
PUD
R/W
0
MCUCR
R
0
R
0
R
0
R
0
• Bit 7 – JTD: JTAG Interface Disable
When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed. If this
bit is one, the JTAG interface is disabled. In order to avoid unintentional disabling or enabling of
the JTAG interface, a timed sequence must be followed when changing this bit: The application
software must write this bit to the desired value twice within four cycles to change its value. Note
that this bit must not be altered when using the On-chip Debug system.
If the JTAG interface is left unconnected to other JTAG circuitry, the JTD bit should be set to
one. The reason for this is to avoid static current at the TDO pin in the JTAG interface.
24.8.2
MCUSR – MCU Status Register
The MCU Status Register provides information on which reset source caused an MCU reset.
Bit
7
–
6
–
5
–
4
3
2
BORF
1
0
0x34 (0x54)
Read/Write
Initial Value
JTRF
R/W
WDRF
R/W
EXTRF
R/W
PORF
R/W
MCUSR
R
0
R
0
R
0
R/W
See Bit Description
• Bit 4 – JTRF: JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by
the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic
zero to the flag.
278
ATmega169P
8018A–AVR–03/06
ATMEL [ ATMEL ]
