13.8 8-bit Timer/Counter Register Description
13.8.1
TCCR0A – Timer/Counter Control Register A
Bit
7
FOC0A
W
6
WGM00
R/W
0
5
COM0A1
R/W
4
COM0A0
R/W
3
WGM01
R/W
0
2
CS02
R/W
0
1
CS01
R/W
0
0
CS00
R/W
0
TCCR0A
0x24 (0x44)
Read/Write
Initial Value
0
0
0
• Bit 7 – FOC0A: Force Output Compare A
The FOC0A bit is only active when the WGM00 bit specifies a non-PWM mode. However, for
ensuring compatibility with future devices, this bit must be set to zero when TCCR0A is written
when operating in PWM mode. When writing a logical one to the FOC0A bit, an immediate com-
pare match is forced on the Waveform Generation unit. The OC0A output is changed according
to its COM0A1:0 bits setting. Note that the FOC0A bit is implemented as a strobe. Therefore it is
the value present in the COM0A1:0 bits that determines the effect of the forced compare.
A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR0A as TOP.
The FOC0A bit is always read as zero.
• Bit 6, 3 – WGM01:0: Waveform Generation Mode
These bits control the counting sequence of the counter, the source for the maximum (TOP)
counter value, and what type of waveform generation to be used. Modes of operation supported
by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and
two types of Pulse Width Modulation (PWM) modes. See Table 13-2 and ”Modes of Operation”
on page 96.
Note:
1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 definitions.
Table 13-2. Waveform Generation Mode Bit Description(1)
WGM01
(CTC0)
WGM00
(PWM0)
Timer/Counter Mode
of Operation
Update of
OCR0A at
TOV0 Flag Set
on
Mode
TOP
0
1
2
3
0
0
1
1
0
1
0
1
Normal
0xFF
0xFF
OCR0A
0xFF
Immediate
TOP
MAX
PWM, Phase Correct
CTC
BOTTOM
MAX
Immediate
TOP
Fast PWM
MAX
However, the functionality and location of these bits are compatible with previous versions of
the timer.
• Bit 5:4 – COM0A1:0: Compare Match Output Mode
These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0
bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin
must be set in order to enable the output driver.
102
ATmega169P
8018A–AVR–03/06
ATMEL [ ATMEL ]
