ATmega16(L)
• MOSI – Port B, Bit 5
MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a
Slave, this pin is configured as an input regardless of the setting of DDB5. When the SPI is
enabled as a Master, the data direction of this pin is controlled by DDB5. When the pin is forced
by the SPI to be an input, the pull-up can still be controlled by the PORTB5 bit.
• SS – Port B, Bit 4
SS: Slave Select input. When the SPI is enabled as a Slave, this pin is configured as an input
regardless of the setting of DDB4. As a Slave, the SPI is activated when this pin is driven low.
When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB4. When
the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB4 bit.
• AIN1/OC0 – Port B, Bit 3
AIN1, Analog Comparator Negative Input. Configure the port pin as input with the internal pull-up
switched off to avoid the digital port function from interfering with the function of the analog
comparator.
OC0, Output Compare Match output: The PB3 pin can serve as an external output for the
Timer/Counter0 Compare Match. The PB3 pin has to be configured as an output (DDB3 set
(one)) to serve this function. The OC0 pin is also the output pin for the PWM mode timer
function.
• AIN0/INT2 – Port B, Bit 2
AIN0, Analog Comparator Positive input. Configure the port pin as input with the internal pull-up
switched off to avoid the digital port function from interfering with the function of the Analog
Comparator.
INT2, External Interrupt Source 2: The PB2 pin can serve as an external interrupt source to the
MCU.
• T1 – Port B, Bit 1
T1, Timer/Counter1 Counter Source.
• T0/XCK – Port B, Bit 0
T0, Timer/Counter0 Counter Source.
XCK, USART External Clock. The Data Direction Register (DDB0) controls whether the clock is
output (DDB0 set) or input (DDB0 cleared). The XCK pin is active only when the USART oper-
ates in Synchronous mode.
and
relate the alternate functions of Port B to the overriding signals shown in
SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal,
while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.
59
2466S–AVR–05/09
ATMEL [ ATMEL CORPORATION ]
