Table 35.
Overriding Signals for Alternate Functions in PC3..PC0
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Note:
PC3/A11
SRE • (XMM<5)
0
SRE • (XMM<5)
1
SRE • (XMM<5)
A11
0
0
–
PC2/A10
SRE • (XMM<6)
0
SRE • (XMM<6)
1
SRE • (XMM<6)
A10
0
0
–
PC1/A9
SRE • (XMM<7)
0
SRE • (XMM<7)
1
SRE • (XMM<7)
A9
0
0
–
PC0/A8
SRE • (XMM<7)
0
SRE • (XMM<7)
1
SRE • (XMM<7)
A8
0
0
–
–
–
–
–
1. XMM = 0 in ATmega103 compatibility mode.
Alternate Functions of
Port D
The Port D pins with alternate functions are shown in
Table 36.
Port D Pins Alternate Functions
Port Pin
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Note:
Alternate Function
T2 (Timer/Counter2 Clock Input)
T1 (Timer/Counter1 Clock Input)
XCK1
(USART1 External Clock Input/Output)
ICP1 (Timer/Counter1 Input Capture Pin)
INT3/TXD1
(External Interrupt3 Input or UART1 Transmit Pin)
INT2/RXD1
(External Interrupt2 Input or UART1 Receive Pin)
INT1/SDA
(External Interrupt1 Input or TWI Serial DAta)
INT0/SCL
(External Interrupt0 Input or TWI Serial CLock)
1. XCK1, TXD1, RXD1, SDA, and SCL not applicable in ATmega103 compatibility mode.
The alternate pin configuration is as follows:
• T2 – Port D, Bit 7
T2, Timer/Counter2 counter source.
• T1 – Port D, Bit 6
T1, Timer/Counter1 counter source.
• XCK1 – Port D, Bit 5
XCK1, USART1 External clock. The Data Direction Register (DDD4) controls whether the clock
is output (DDD4 set) or input (DDD4 cleared). The XCK1 pin is active only when the USART1
operates in Synchronous mode.
78
ATmega128
2467S–AVR–07/09
ATMEL [ ATMEL CORPORATION ]
