ATmega128(L)
Asynchronous Timer
Clock – clkASY
The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly
from an external 32 kHz clock crystal. The dedicated clock domain allows using this
Timer/Counter as a real-time counter even when the device is in sleep mode.
ADC Clock – clkADC
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks
in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion
results.
XTAL Divide Control
Register – XDIV
The XTAL Divide Control Register is used to divide the Source clock frequency by a number in
the range 2 - 129. This feature can be used to decrease power consumption when the require-
ment for processing power is low.
Bit
7
XDIVEN
R/W
0
6
XDIV6
R/W
0
5
XDIV5
R/W
0
4
XDIV4
R/W
0
3
XDIV3
R/W
0
2
XDIV2
R/W
0
1
XDIV1
R/W
0
0
XDIV0
R/W
0
XDIV
Read/Write
Initial Value
• Bit 7 – XDIVEN: XTAL Divide Enable
When the XDIVEN bit is written one, the clock frequency of the CPU and all peripherals (clkI/O,
clkADC, clkCPU, clkFLASH) is divided by the factor defined by the setting of XDIV6 - XDIV0. This bit
can be written run-time to vary the clock frequency as suitable to the application.
• Bits 6..0 – XDIV6..XDIV0: XTAL Divide Select Bits 6 - 0
These bits define the division factor that applies when the XDIVEN bit is set (one). If the value of
these bits is denoted d, the following formula defines the resulting CPU and peripherals clock
frequency fCLK
:
Source clock
f
= ---------------------------------
CLK
129 – d
The value of these bits can only be changed when XDIVEN is zero. When XDIVEN is written to
one, the value written simultaneously into XDIV6..XDIV0 is taken as the division factor. When
XDIVEN is written to zero, the value written simultaneously into XDIV6..XDIV0 is rejected. As
the divider divides the master clock input to the MCU, the speed of all peripherals is reduced
when a division factor is used.
When the system clock is divided, Timer/Counter0 can be used with Asynchronous clock only. The fre-
quency of the asynchronous clock must be lower than 1/4th of the frequency of the scaled down Source
clock. Otherwise, interrupts may be lost, and accessing the Timer/Counter0 registers may fail.
Clock Sources
The device has the following clock source options, selectable by Flash fuse bits as shown
below. The clock from the selected source is input to the AVR clock generator, and routed to the
appropriate modules.
Table 6. Device Clocking Options Select
Device Clocking Option
CKSEL3..0(1)
1111 - 1010
1001
External Crystal/Ceramic Resonator
External Low-frequency Crystal
37
2467P–AVR–08/07
ATMEL [ ATMEL ]
