ATmega640/1280/1281/2560/2561
Table 31-13. External Data Memory Characteristics, 2.7 - 5.5 Volts, No Wait-state (Continued)
4 MHz Oscillator Variable Oscillator
Min Max
Symbol
Parameter
Min
Max
Unit
Address Hold after ALE Low,
read access
3b tLLAX_LD
5
5
ns
4
5
6
7
8
9
tAVLLC
tAVRL
tAVWL
tLLWL
tLLRL
Address Valid C to ALE Low
Address Valid to RD Low
Address Valid to WR Low
ALE Low to WR Low
ALE Low to RD Low
115
235
235
115
115
45
0.5tCLCL-10(1)
1.0tCLCL-15
1.0tCLCL-15
0.5tCLCL-10(2)
0.5tCLCL-10(2)
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
130
130
0.5tCLCL+5(2)
0.5tCLCL+5(2)
tDVRH
Data Setup to RD High
Read Low to Data Valid
Data Hold After RD High
RD Pulse Width
10 tRLDV
11 tRHDX
12 tRLRH
13 tDVWL
14 tWHDX
15 tDVWH
16 tWLWH
190
1.0tCLCL-60
0
0
235
105
235
250
235
1.0tCLCL-15
0.5tCLCL-20(1)
1.0tCLCL-15
1.0tCLCL
Data Setup to WR Low
Data Hold After WR High
Data Valid to WR High
WR Pulse Width
1.0tCLCL-15
Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.
2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.
Table 31-14. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 0, SRWn0 = 1
4 MHz Oscillator
Variable Oscillator
Min Max
Symbol
Parameter
Min
Max
Unit
MHz
ns
0
1/tCLCL
Oscillator Frequency
Read Low to Data Valid
RD Pulse Width
0.0
8
10 tRLDV
12 tRLRH
15 tDVWH
16 tWLWH
440
2.0tCLCL-60
485
500
485
2.0tCLCL-15
2.0tCLCL
ns
Data Valid to WR High
WR Pulse Width
ns
2.0tCLCL-15
ns
Table 31-15. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0
4 MHz Oscillator Variable Oscillator
Symbol
Parameter
Min
Max
Min
Max
8
Unit
MHz
ns
0
1/tCLCL
Oscillator Frequency
Read Low to Data Valid
RD Pulse Width
0.0
10 tRLDV
12 tRLRH
15 tDVWH
16 tWLWH
690
3.0tCLCL-60
735
750
735
3.0tCLCL-15
3.0tCLCL
ns
Data Valid to WR High
WR Pulse Width
ns
3.0tCLCL-15
ns
383
2549L–AVR–08/07
ATMEL [ ATMEL ]
