ATmega640/1280/1281/2560/2561
Table 31-8. ADC Characteristics, Differential Channels (Continued)
Symbol Parameter Condition
Min(1)
CC - 0.3
2.7
Typ(1)
Max(1)
VCC + 0.3
AVCC - 0.5
VCC
Units
V
AVCC
VREF
VIN
Analog Supply Voltage
V
Reference Voltage
Input Voltage
V
GND
V
VDIFF
Input Differential Voltage
ADC Conversion Output
Input Bandwidth
-VREF/Gain
-511
VREF/Gain
511
V
LSB
kHz
V
4
VINT
RREF
RAIN
Internal Voltage Reference
Reference Input Resistance
Analog Input Resistance
Values are guidelines only.
2.3
2.56
32
2.8
kΩ
MΩ
100
Note:
31.9 External Data Memory Timing
Table 31-9. External Data Memory Characteristics, 4.5 - 5.5 Volts, No Wait-state
8 MHz Oscillator
Variable Oscillator
Symbol
1/tCLCL
tLHLL
Parameter
Min
Max
Min
Max
Unit
MHz
ns
0
1
2
Oscillator Frequency
ALE Pulse Width
0.0
16
115
1.0tCLCL-10
0.5tCLCL-5(1)
tAVLL
Address Valid A to ALE Low
57.5
ns
Address Hold After ALE Low,
write access
3a
3b
tLLAX_ST
tLLAX_LD
5
5
5
ns
ns
Address Hold after ALE Low,
read access
5
4
tAVLLC
tAVRL
tAVWL
tLLWL
tLLRL
Address Valid C to ALE Low
Address Valid to RD Low
Address Valid to WR Low
ALE Low to WR Low
ALE Low to RD Low
57.5
115
115
47.5
47.5
40
0.5tCLCL-5(1)
1.0tCLCL-10
1.0tCLCL-10
0.5tCLCL-15(2)
0.5tCLCL-15(2)
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
6
7
67.5
67.5
0.5tCLCL+5(2)
0.5tCLCL+5(2)
8
9
tDVRH
tRLDV
tRHDX
tRLRH
tDVWL
tWHDX
tDVWH
tWLWH
Data Setup to RD High
Read Low to Data Valid
Data Hold After RD High
RD Pulse Width
10
11
12
13
14
15
16
75
1.0tCLCL-50
0
0
115
42.5
115
125
115
1.0tCLCL-10
0.5tCLCL-20(1)
1.0tCLCL-10
1.0tCLCL
Data Setup to WR Low
Data Hold After WR High
Data Valid to WR High
WR Pulse Width
1.0tCLCL-10
Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.
381
2549L–AVR–08/07
ATMEL [ ATMEL ]
