ATmega640/1280/1281/2560/2561
Table 30-14. Parallel Programming Characteristics, VCC = 5V 10% (Continued)
Symbol
tXLWL
tXLPH
Parameter
Min
0
Typ
Max
Units
ns
XTAL1 Low to WR Low
XTAL1 Low to PAGEL high
PAGEL low to XTAL1 high
BS1 Valid before PAGEL High
PAGEL Pulse Width High
BS1 Hold after PAGEL Low
BS2/1 Hold after WR Low
PAGEL Low to WR Low
BS2/1 Valid to WR Low
WR Pulse Width Low
0
ns
tPLXH
150
67
150
67
67
67
67
150
0
ns
tBVPH
tPHPL
ns
ns
tPLBX
ns
tWLBX
tPLWL
tBVWL
tWLWH
tWLRL
tWLRH
tWLRH_CE
tXLOL
ns
ns
ns
ns
WR Low to RDY/BSY Low
WR Low to RDY/BSY High(1)
WR Low to RDY/BSY High for Chip Erase(2)
XTAL1 Low to OE Low
1
4.5
9
μs
ms
ms
ns
3.7
7.5
0
tBVDV
tOLDV
tOHDZ
BS1 Valid to DATA valid
OE Low to DATA Valid
0
250
250
250
ns
ns
OE High to DATA Tri-stated
ns
Notes: 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits
commands.
2.
tWLRH_CE is valid for the Chip Erase command.
30.8 Serial Downloading
Both the Flash and EEPROM memory arrays can be programmed using a serial programming
bus while RESET is pulled to GND. The serial programming interface consists of pins SCK, PDI
(input) and PDO (output). After RESET is set low, the Programming Enable instruction needs to
be executed first before program/erase operations can be executed. NOTE, in Table 30-15 on
page 351, the pin mapping for serial programming is listed. Not all packages use the SPI pins
dedicated for the internal Serial Peripheral Interface - SPI.
30.8.1
Serial Programming Pin Mapping
Table 30-15. Pin Mapping Serial Programming
Pins
Pins
Symbol
PDI
(TQFP-100)
(TQFP-64)
I/O
Description
Serial Data in
Serial Data out
Serial Clock
PB2
PB3
PB1
PE0
I
O
I
PDO
SCK
PE1
PB1
Figure 30-9. Serial Programming and Verify(1)
351
2549L–AVR–08/07
ATMEL [ ATMEL ]
