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ATMEGA2560-16AU-SL383 参数 Datasheet PDF下载

ATMEGA2560-16AU-SL383图片预览
型号: ATMEGA2560-16AU-SL383
PDF下载: 下载PDF文件 查看货源
内容描述: [Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 16MHz, CMOS, PQFP100, 14 X 14 MM, 1 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, MS-026AED, TQFP-100]
分类和应用: 时钟微控制器
文件页数/大小: 448 页 / 7518 K
品牌: ATMEL [ ATMEL ]
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7.6.1  
RAMPZ – Extended Z-pointer Register for ELPM/SPM  
Bit  
7
6
5
4
3
2
1
0
RAMPZ7  
RAMPZ6  
RAMPZ5  
RAMPZ4  
RAMPZ3  
RAMPZ2  
RAMPZ1  
RAMPZ0  
0x3B (0x5B)  
Read/Write  
Initial Value  
RAMPZ  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
0
0
0
0
0
0
0
0
For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown  
in Figure 7-4. Note that LPM is not affected by the RAMPZ setting.  
Figure 7-4. The Z-pointer used by ELPM and SPM  
Bit (  
Individually)  
7
0
7
0
8
7
7
0
0
RAMPZ  
ZH  
ZL  
Bit (Z-pointer)  
23  
16  
15  
The actual number of bits is implementation dependent. Unused bits in an implementation will  
always read as zero. For compatibility with future devices, be sure to write these bits to zero.  
7.6.2  
EIND – Extended Indirect Register  
Bit  
0x3C (0x5C)  
7
6
EIND6  
R/W  
0
5
EIND5  
R/W  
0
4
EIND4  
R/W  
0
3
EIND3  
R/W  
0
2
EIND2  
R/W  
0
1
EIND1  
R/W  
0
0
EIND0  
R/W  
0
EIND7  
EIND  
Read/Write  
R/W  
Initial Value  
0
For EICALL/EIJMP instructions, the Indirect-pointer to the subroutine/routine is a concatenation  
of EIND, ZH, and ZL, as shown in Figure 7-5. Note that ICALL and IJMP are not affected by the  
EIND setting.  
Figure 7-5. The Indirect-pointer used by EICALL and EIJMP  
Bit (Individual-  
ly)  
7
0
7
0
7
7
0
0
EIND  
ZH  
ZL  
Bit (Indirect-  
pointer)  
23  
16  
15  
8
The actual number of bits is implementation dependent. Unused bits in an implementation will  
always read as zero. For compatibility with future devices, be sure to write these bits to zero.  
7.7  
Instruction Execution Timing  
This section describes the general access timing concepts for instruction execution. The AVR  
CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the  
chip. No internal clock division is used.  
Figure 7-6 shows the parallel instruction fetches and instruction executions enabled by the Har-  
vard architecture and the fast-access Register File concept. This is the basic pipelining concept  
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,  
functions per clocks, and functions per power-unit.  
16  
ATmega640/1280/1281/2560/2561  
2549L–AVR–08/07  
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