Table 3-1.
Pin Name
Signal Description by Peripheral
Function
SPI
Type
Active
Level
Comments
MISO
MOSI
SPCK
NPCS0
NPCS1 - NPCS3
Master In Slave Out
Master Out Slave In
SPI Serial Clock
SPI Peripheral Chip Select 0
SPI Peripheral Chip Select
Two-Wire Interface
I/O
I/O
I/O
I/O
Output
Low
Low
TWD
TWCK
Two-wire Serial Data
Two-wire Serial Clock
I/O
I/O
4. Package and Pinout
The AT91RM9200 is available in two packages:
• 208-pin PQFP, 31.2 x 31.2 mm, 0.5 mm pitch
• 256-ball BGA, 15 x 15 mm, 0.8 mm ball pitch
The product features of the 256-ball BGA package are extended compared to the 208-lead
PQFP package. The features that are available only with the 256-ball BGA package are:
• Parallel I/O Controller D
• ETM
™
port with outputs multiplexed on the PIO Controller D
• a second USB Host transceiver, opening the Hub capabilities of the embedded USB Host.
4.1
208-pin PQFP Package Outline
shows the orientation of the 208-pin PQFP package.
A detailed mechanical description is given in the section “AT91RM9200 Mechanical Characteris-
tics” of the product datasheet.
Figure 4-1.
208-pin PQFP Package (Top View)
156
157
105
104
208
1
52
53
8
AT91RM9200
1768G–ATARM–29-Sep-06
ATMEL [ ATMEL CORPORATION ]
