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AT90PWM3B-16SU 参数 Datasheet PDF下载

AT90PWM3B-16SU图片预览
型号: AT90PWM3B-16SU
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器具有8K字节的系统内可编程闪存 [8-bit Microcontroller with 8K Bytes In-System Programmable Flash]
分类和应用: 闪存微控制器
文件页数/大小: 361 页 / 6022 K
品牌: ATMEL [ ATMEL ]
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The comparator output toggles at the comparator clock frequency when the voltage differ-  
ence between both inputs is lower than the offset. This may occur when comparing signal  
with small slew rate.  
Work around:  
This effect normally do not impact the PSC, as the transition is sampled once per PSC cycle  
Be carefull when using the comparator as an interrupt source.  
15. PSC : Autolock mode  
This mode is not properly handled when CLKPSC is different from CLK IO.  
Work around:  
With CLKPSC equals 64/32 MHz (CLKPLL), use LOCK mode  
16. DALI : 17th bit detection  
17th bit detection do not occurs if the signal arrives after the sampling point.  
Workaround:  
Use this feature only for sofware development and not in field conditions  
17. PSC : One ramp mode with PSC input mode 8  
The retriggering is not properly handled in this case.  
Work around:  
Do not program this case.  
18. PSC : Desactivation of outputs in mode 14  
See “PSC Input Mode 14: Fixed Frequency Edge Retrigger PSC and Disactivate Output” on  
page 154.  
Work around:  
Do not use this mode to desactivate output if retrigger event do not occurs during On-Time.  
32.2 AT90PWM2B/3B  
PSC : Double End-Of-Cycle Interrupt Request in Centered Mode  
ADC : Conversion accuracy  
1. PSC : Double End-Of-Cycle Interrupt Request in Centered Mode  
In centered mode, after the “expected” End-Of-Cycle Interrupt, a second unexpected Inter-  
rupt occurs 1 PSC cycle after the previous interrupt.  
Work around:  
While CPU cycle is lower than PSC clock, the CPU sees only one interrupt request. For PSC  
clock period greater than CPU cycle, the second interrupt request must be cleared by  
software.  
2. ADC : Conversion accuracy  
The conversion accuracy degrades when the ADC clock is 2 MHz.  
Work around:  
When a 10 bit conversion accuracy is required, use an ADC clock of 1 MHz or below.  
At 2 Mhz the ADC can be used as a 7 bits ADC.  
3. DAC Driver linearity above 3.6V  
With 5V Vcc, the DAC driver linearity is poor when DAC output level is above Vcc-1V. At 5V,  
DAC output for 1023 will be around 5V - 40mV.  
Work around: .  
350  
AT90PWM2/3/2B/3B  
4317J–AVR–08/10  
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