AT89S52
frequency should be less than 1/16 of the crystal fre-
quency. With a 33 MHz oscillator clock, the maximum SCK
frequency is 2 MHz.
appropriate Write instruction. The write cycle is self-
timed and typically takes less than 1 ms at 5V.
4. Any memory location can be verified by using the
Read instruction which returns the content at the
selected address at serial output MISO/P1.6.
Serial Programming Algorithm
5. At the end of a programming session, RST can be
set low to commence normal device operation.
To program and verify the AT89S52 in the serial program-
ming mode, the following sequence is recommended:
Power-off sequence (if needed):
Set XTAL1 to “L” (if a crystal is not used).
Set RST to “L”.
1. Power-up sequence:
Apply power between VCC and GND pins.
Set RST pin to “H”.
Turn VCC power off.
If a crystal is not connected across pins XTAL1 and
XTAL2, apply a 3 MHz to 33 MHz clock to XTAL1 pin
and wait for at least 10 milliseconds.
Data Polling: The Data Polling feature is also available in
the serial mode. In this mode, during a write cycle an
attempted read of the last byte written will result in the com-
plement of the MSB of the serial output byte on MISO.
2. Enable serial programming by sending the Pro-
gramming Enable serial instruction to pin
MOSI/P1.5. The frequency of the shift clock sup-
plied at pin SCK/P1.7 needs to be less than the
CPU clock at XTAL1 divided by 16.
Serial Programming Instruction Set
The Instruction Set for Serial Programming follows a 4-byte
protocol and is shown in Table 10.
3. The Code array is programmed one byte at a time
by supplying the address and data together with the
17
ATMEL [ ATMEL ]
