AT89C2051x2
Idle Mode
In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active.
The mode is invoked by software. The content of the on-chip RAM and all the special
functions registers remain unchanged during this mode. The idle mode can be termi-
nated by any enabled interrupt or by a hardware reset.
P1.0 and P1.1 should be set to “0” if no external pull-ups are used, or set to “1” if
external pull-ups are used.
It should be noted that when idle is terminated by a hardware reset, the device normally
resumes program execution, from where it left off, up to two machine cycles before the
internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM
in this event, but access to the port pins is not inhibited. To eliminate the possibility of an
unexpected write to a port pin when Idle is terminated by reset, the instruction following
the one that invokes Idle should not be one that writes to a port pin or to external
memory.
Power-down Mode
In the power-down mode the oscillator is stopped, and the instruction that invokes
power-down is the last instruction executed. The on-chip RAM and Special Function
Registers retain their values until the power-down mode is terminated. The only exit
from power-down is a hardware reset. Reset redefines the SFRs but does not change
the on-chip RAM. The reset should not be activated before V
CC
is restored to its normal
operating level and must be held active long enough to allow the oscillator to restart and
stabilize.
P1.0 and P1.1 should be set to “0” if no external pull-ups are used, or set to “1” if
external pull-ups are used.
Programming
the Flash
The AT89C2051x2 is shipped with the 2K bytes of on-chip Flash code memory array in
the erased state (i.e., contents = FFH) and ready to be programmed. The code memory
array is programmed one byte at a time.
Once the array is programmed, to re-program
any non-blank byte, the entire memory array needs to be erased electrically.
Internal Address Counter:
The AT89C2051x2 contains an internal memory address
counter which is always reset to 000H on the rising edge of RST and is advanced by
applying a positive going pulse to pin XTAL1.
Programming Algorithm:
To program the AT89C2051x2, the following sequence is
recommended.
1. Power-up sequence:
Apply power between V
CC
and GND pins
Set RST and XTAL1 to GND
2. Set pin RST to “H”
Set pin P3.2 to “H”
3. Apply the appropriate combination of “H” or “L” logic
levels to pins P3.3, P3.4, P3.5, P3.7 to select one of the programming operations
shown in the Flash Programming Modes table.
To Program and Verify the Array:
1. Apply data for Code byte at location 000H to P1.0 to P1.7.
2. Raise RST to 12V to enable programming.
3. Pulse P3.2 once to program a byte in the program memory array or the lock bits.
The byte-write cycle is self-timed and typically takes 1.2 ms.
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3285B–MICRO–10/03
ATMEL [ ATMEL CORPORATION ]
